X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to; bh=pab9qzDl0c8zV28+ANf8+FWv7VXCTDUl61UbHdeEzFg=; b=ECPOayWM/35wDPe1gL2ZK0UMAet5bUMqkV1YmIXT9DwPpkx3x4vKb/0K4/ug97POi7 HMTh1/x1g44u8kxtuWpKX1CN+OuAwVYthm+TpWvIfn1qVmn7iZCZRcLScocWRCJQJcvW txC7dhjsNYAh/s8n2c9Uez+S/B4wr/0HVJwDZLwJYkQ0W3Yi59kIWyg3kduf0gBmDGWy mKZeuAdb/bFsPEDThqbcWWbaTiE5VFIyUNri8t+vblf9acoyVuHyeZ/gETPxSZQUj/Hz G4fBDotSEtOgiSgF9cJ7tIBh+394DiwBJ+BOpVJ+m/ncDq3clVYCAl/PERgO4O280siV HIcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=pab9qzDl0c8zV28+ANf8+FWv7VXCTDUl61UbHdeEzFg=; b=RFCt8moLundIIXeWWbgZpILTmII8iWlXK6cs2SnNiUXxqzUkh56zxgu17+5CFUdlsY 7qGEWEmy4P76g1Bj7LQIK5sNBFd+Ojl4dKeYd/1lpQ66B1/lnGd4LSdPPRVsKq5Fxh85 MRD5i/Y7rXjm6bN58pAFT2u6ppZhPNnC3XQCDwx/fqcx/WYnzLt/oUQjBfq6EDvDy7Fa e60K2DaHxbSk4N4BZPv+V78JdpUKCqNUZzjtzE9p5x2vjvO3Ty8zNjBprtjbFIj2vDGz OVAUyb54TTo7QH8JhHvMRyMC0QCtB3Kg+1aGS/ousPIB8xw7KIeOPhf+LwCqP2+oXPFN coww== X-Gm-Message-State: AIkVDXK1NEMwexxVJU7/Gvqgx2T2IhGZWVHE6LbZuOyGzevd2oO4yK5tjsZTiaZ5+Jvi4zFhfmGiCNvWyK2OHg== X-Received: by 10.31.73.198 with SMTP id w189mr1104572vka.170.1484737726890; Wed, 18 Jan 2017 03:08:46 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: From: "Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" Date: Wed, 18 Jan 2017 12:08:46 +0100 Message-ID: Subject: Re: [geda-user] [pcb] why no clearpoly on silk To: geda-user AT delorie DOT com Content-Type: multipart/alternative; boundary=001a114d5d4ccbc67005465c707d Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk --001a114d5d4ccbc67005465c707d Content-Type: text/plain; charset=UTF-8 Maybe I got something wrong. Normally clearance is between copper while the silk is painted on both? 2017-01-18 11:54 GMT+01:00 Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com] : > > > On 18 Jan 2017 10:38, wrote > > > Given the abundance of existing designs, you might cause silk layer >> breakage >> if you suddenly enable clipping there... unless we also special cased >> turning off the flags enabling clearance when drawing / moving new lines >> on >> the silk layers? >> > > Just to be clear on this, I do not propose any change for mainline for > this. > > > No, but it's one worth considering if it can be done in a way that > preserves behaviour of existing files. > > I'd like to try to keep compatibility with pcb-rnd where we can, and there > seems no real point in reinventing different ways to make the same > improvements. > > (Btw.. Would dearly love to kill off debug draw in mainline too, as it's a > nuisance) > > In pcb-rnd we have support for multiple board file formats. Our native > format is not pcb but lihata. We support pcb as we support kicad's format. > The native format supports all features, but the non-native ones don't. > > > Point me at the libhata docs at some point if you get a chance? > > > So my removal of this restriction in pcb-rnd would do something like this: > > - if silk polys are loaded from .pcb, I'd remove the clearpoly flag; I > think this would restore the original behaviour on load. > > > I think so. > > - when silk poly is saved to .pcb, maybe I should put there the clearpoly > flag, as that's how silk poly exists naturally - but I am not sure about > this part yet > > > I guess one way might to have a test for version (or flag) that allows to > know if the data inside the file is supposed to be correct or not. > > Could do it on version, assuming you reset the relevant flags on any file > loaded before that version number was set. > > > - same rules apply to curret (then-old) version of the lihata format > > - I'd bump the version of the lihata board format and the new version > wouldn't manipulate the silk poly flags on load or save > > > Do you think this could work? > > > Sounds workable to me. > > I'm still trying to recall if the clipper always worked this way, or > whether it was a dumb change I introduced in an attempt to speed up cutting > to a buffer or something. > > I don't "think" the silk lines ever used to clear, but I could be wrong. > I'd bet historically, the behaviour goes back to before the clipper - when > clearances in planes were drawn in negative on polygons directly from > bloated track geometry. > > > Peter > --001a114d5d4ccbc67005465c707d Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Maybe I got something wrong. Normally clearance is between= copper while the silk is painted on both?
=
2017-01-18 11:54 GMT+01:00 Peter Clifton (petercjclifton AT googlemail DOT co= m) [via geda-user AT delorie DOT com<= /a>] <geda-user AT delorie DOT com>:


=
On 18 Jan 2017 10:38, <gedau AT igor2 DOT repo DOT hu> wrote

Given the abundance of existing designs, you might cause silk layer breakag= e
if you suddenly enable clipping there... unless we also special cased
turning off the flags enabling clearance when drawing / moving new lines on=
the silk layers?

Just to be clear on this, I do not propose any change for mainline for this= .

No, but it's one worth considering if it can be done in a way= that preserves behaviour of existing files.

I'd like to try to keep compatibility with pcb-rnd= where we can, and there seems no real point in reinventing different ways = to make the same improvements.

(Btw.. Would dearly love to kill off debug draw in mainline too, as = it's a nuisance)

In pcb-rnd we have support for multiple board file formats. Our native form= at is not pcb but lihata. We support pcb as we support kicad's format. = The native format supports all features, but the non-native ones don't.=

Point me at the libhata docs at some point if you get a chance?


<= div class=3D"gmail_extra" dir=3D"auto">
So my removal of this restriction in pcb-rnd would do something like this:<= br>
- if silk polys are loaded from .pcb, I'd remove the clearpoly flag; I = think this would restore the original behaviour on load.

I think so.<= /div>

- when silk poly is saved to .pcb, maybe I should put there the clearpoly f= lag, as that's how silk poly exists naturally - but I am not sure about= this part yet

I guess one way might to have a test for version (or f= lag) that allows to know if the data inside the file is supposed to be corr= ect or not.

Could do it = on version, assuming you reset the relevant flags on any file loaded before= that version number was set.

<= /div>

- same rules apply to curret (then-old) version of the lihata format

- I'd bump the version of the lihata board format and the new version w= ouldn't manipulate the silk poly flags on load or save


Do you think this could work?

Sounds workable to me.

I'm still trying to recall if the cl= ipper always worked this way, or whether it was a dumb change I introduced = in an attempt to speed up cutting to a buffer or something.

I don't "think" the sil= k lines ever used to clear, but I could be wrong. I'd bet historically,= the behaviour goes back to before the clipper - when clearances in planes = were drawn in negative on polygons directly from bloated track geometry.


Peter
<= /div>

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