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Date: Mon, 4 Jan 2016 14:12:48 +0000
Message-ID: <CAJXU7q_H54n7-iyephsGF8DnSvu2f1zv_jqkFsthDwVCVa7BnQ@mail.gmail.com>
Subject: Re: [geda-user] Project leadership
From: "Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On 4 Jan 2016 14:00, "Roland Lutz" <rlutz AT hedmen DOT org> wrote:

> Thinking about it, I'm not even sure if this behavior (treating the slots
of a package as individual SPICE objects) is even necessary.  The other
SPICE backends don't seem to be using it.

An alternative option would be to have a (schematic or netlist based)
sub-model which maps the connections of the actual part, to 'n' internal
instances of the cell model.

It really depends on whether you are viewing the schematic and spice
simulation as that of the design with actual parts, or at a more abstracted
level where actual embodiment of the opamp cells means picking what chip
they go in.

At a detailed level, the physical model can include more parasitics at
physically representitive points in the model.

Seems similar in some way to the differences between simulating your VHDL /
verilog as written (perhaps with timing back annotated), vs. simulating the
synthesised netlist.

Usually we don't have a synthesize or map step in the schematic to pcb
workflow of course!

Peter

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<p dir=3D"ltr"><br>
On 4 Jan 2016 14:00, &quot;Roland Lutz&quot; &lt;<a href=3D"mailto:rlutz AT he=
dmen.org">rlutz AT hedmen DOT org</a>&gt; wrote:</p>
<p dir=3D"ltr">&gt; Thinking about it, I&#39;m not even sure if this behavi=
or (treating the slots of a package as individual SPICE objects) is even ne=
cessary.=C2=A0 The other SPICE backends don&#39;t seem to be using it.<br><=
/p>
<p dir=3D"ltr">An alternative option would be to have a (schematic or netli=
st based) sub-model which maps the connections of the actual part, to &#39;=
n&#39; internal instances of the cell model.</p>
<p dir=3D"ltr">It really depends on whether you are viewing the schematic a=
nd spice simulation as that of the design with actual parts, or at a more a=
bstracted level where actual embodiment of the opamp cells means picking wh=
at chip they go in.</p>
<p dir=3D"ltr">At a detailed level, the physical model can include more par=
asitics at physically representitive points in the model.</p>
<p dir=3D"ltr">Seems similar in some way to the differences between simulat=
ing your VHDL / verilog as written (perhaps with timing back annotated), vs=
. simulating the synthesised netlist.</p>
<p dir=3D"ltr">Usually we don&#39;t have a synthesize or map step in the sc=
hematic to pcb workflow of course!</p>
<p dir=3D"ltr">Peter</p>

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