On Oct 24, 2015, at 11:57 AM, Britton = Kerin (britton DOT kerin AT gmail DOT com) = [via geda-user AT delorie DOT com] = <geda-user AT delorie DOT com>= wrote:

On Fri, Oct 23, 2015 at 9:10 PM, DJ Delorie <dj AT delorie DOT com> wrote:

> IIRC at the moment it give NO WARNING for duplicate refdes, which = is just
> inexcusable. To be fair you can blame this on pcb but = still...

It's common to break large chips (like MCUs) into separate = symbols to
manage them better, which means that a duplicate refdes is allowed = (in
fact, required) in those cases.

If you stop using separate pages, you'll stop wanting to do = that. I use beaglebone symbols, they are large and square but so = what?

For big = projects, schematics wind up in printable documentation for reviewers, = layout engineers, fabricators, test engineers, and technicians. = Sometimes this is a contractual requirement. I like to weave some = explanatory text around them, too. My colleagues/customers seem to like = this, although one colleague jokes that I apparently love writing = masters=92 theses.

I sometimes use big symbols = on extensive sheets, but then things get unreadable on letter or A4 = paper. I do projects on all scales with gEDA, from little tests of = breadboard ideas (another joke is that I love doing science fair = projects) to multi-board systems with thousands of components. There is = not a single style for all purposes. The fact that gEDA does not enforce = any particular style is a good thing.

What should not be allowed is duplicate pins, module how slotting is
implemented. The problem I forsee is that "duplicate pins" is = a
problem that will be solved in the netlister *if* slotting is moved
out of gschem, resulting in duplicates being allowed in gschem,
resulting in ambiguity.

So there's three cases:

1. One symbol to one component, refdes should be unique, no problem.

2. Many symbols to one component (MCU), refdes must be same but pins
should be unique.

One way would be to require symbols that want to do this to = have a "part_of=3Dsomething_real" attribute. They could then work = with warning on. Warning could be enabled by default, and parts = still portable to instances with the default = behavior.

It = can get tricky. There may be multiple ways to partition a package. = Consider an MCU whose internal peripherals use multiplexed pins: you = might want a symbol per peripheral, but you can=92t use every peripheral = in a design. I=92ve heard of one prominent developer/user employing = redundant slots to implement pin swaps. We have a lot of = freedom.

I think a rather robust way to detect = problems with packages composed of multiple symbols is to check that all = pins are represented exactly once. Some symbols in the standard gEDA = library have a pins=3D attribute, so there=92s a precedent for providing = the required information. If it=92s absent, schema that standard gEDA = footprints use makes the pin count easy to decode. This is another = problem that looks much simpler from the bottom up (what is actually = implemented?) than from the top down (are the user=92s intentions = consistent?).

3. Many symbols to one component (SLOTTING), refdes and pins may be = be
same or unique depending on how slotting is = implemented.

Hmm, since = my inclination here is to have Q1 refer to a particular transistor = rather than a part, I guess I have to acknowledge = inconsistency.
In practice I've avoided slotting = entirely out of fear and just made e.g. multi-amp symbols when = needed. To be honest I can't imagine how to make slotting and = subcircs work together gracefully.

> Schematic pages except for subcircs are obsolete IMO,

I use separate pages because I often implement subcircuits = separately
for testing. For example, I might fab just the power supply. = In my
powermeter board, 15 of the 16 channel circuits were implemented = with
a script that copied the first channel's = page.

Same here. My = point was that when you do subcirc pages they get their own refdes = space, so the fact that gschem can't check for inter-page uniqueness = isn't = relevant.

When I = wrote gnet-spice-noqsi, I didn=92t anticipate how it would change my = design flow. It can generate a subcircuit from the same symbol/attribute = conventions that the gnetlist core uses when expanding hierarchy. As a = consequence, it is very convenient to make the first draft of a = subsystem as a subcircuit. It=92s much handier to instantiate the = subsystem in a test schematic of SPICE-specific components than to mix = SPICE components with physical components. One result is that my top = level schematics look more like block diagrams.

> If you need to print your schematics it's because your CAD = sucks
> somehow.

Or because you want to debug and the bench doesn't have its = own
monitor. Or because you're writing an article and need the = schematic

Time for a new = bench :)