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Date: Sun, 27 Oct 2013 21:16:33 +0430
Message-ID: <CANhYM9HBm2Z+M07uNCSayiA_Ua+_x3-gezXA7cozRnthwjRaqA@mail.gmail.com>
Subject: Re: [geda-user] Power to ICs with numslots > 1
From: James Jackson <james DOT a DOT f DOT jackson DOT 2 AT googlemail DOT com>
To: geda-user AT delorie DOT com
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Further to this, looking in the PCB Netlist dialog, I see that each of my
subcircuits also contains duplicate nets (i.e. for +15v, 0v etc).

How can I get gsch2pcb to merge given nets (as well as ICs, as above)
across subcircuits?

Many thanks,
James.


On Sun, Oct 27, 2013 at 9:04 PM, James Jackson <
james DOT a DOT f DOT jackson DOT 2 AT googlemail DOT com> wrote:

> Hi all,
>
> Many thanks for this - I've now got a fairly hefty multi-page schematic
> drawn up (using the source=x attribute to link subcircuits to a master
> sheet with the signal routes between subcircuits), with a separate
> schematic for power rails.
>
> I now have a problem when I run gsch2pcb - the 'split' ICs with the same
> refdes (i.e. power in subcircuit 1 (refdes SS1), signal in subcircuit 2
> (refdes SS2)) are being placed twice on my PCB, with names SS1/U1 and
> SS2/U1.
>
> How can I force gsch2pcb to 'do the right thing' here?
>
> Many thanks,
> James.
>
>
> On Sun, Oct 27, 2013 at 8:57 AM, Dave Curtis <davecurtis AT sonic DOT net> wrote:
>
>> On 10/26/2013 12:08 PM, DJ Delorie wrote:
>>
>>> Typically, you'd have a separate symbol that had *only* the two power
>>> pins, and the same refdes.  The netlister will merge those pins with
>>> the slotted pins when the schematic is exported.
>>>
>>>  That is exactly what I do.  It leads to cleaner schematics.  You can
>> put the functional data flow on functional sheets, and infrastructure on
>> infrastructure sheets, and neither clutters the other.  It makes schematics
>> much more readable.
>>
>> In these days of mixed voltages all over the place, having implicit power
>> connections just leads to confusion and bugs.  Better to show it all
>> explicitly, IMCO (In my curmudgeonly opinion).
>>
>> -dave
>>
>>
>

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<div dir=3D"ltr">Further to this, looking in the PCB Netlist dialog, I see =
that each of my subcircuits also contains duplicate nets (i.e. for +15v, 0v=
 etc).<div><br></div><div>How can I get gsch2pcb to merge given nets (as we=
ll as ICs, as above) across subcircuits?</div>
<div><br></div><div>Many thanks,</div><div>James.</div></div><div class=3D"=
gmail_extra"><br><br><div class=3D"gmail_quote">On Sun, Oct 27, 2013 at 9:0=
4 PM, James Jackson <span dir=3D"ltr">&lt;<a href=3D"mailto:james.a.f.jacks=
on DOT 2 AT googlemail DOT com" target=3D"_blank">james DOT a DOT f DOT jackson DOT 2 AT googlemail DOT com</=
a>&gt;</span> wrote:<br>
<blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1p=
x #ccc solid;padding-left:1ex"><div dir=3D"ltr">Hi all,<br><div><br></div><=
div>Many thanks for this - I&#39;ve now got a fairly hefty multi-page schem=
atic drawn up (using the source=3Dx attribute to link subcircuits to a mast=
er sheet with the signal routes between subcircuits), with a separate schem=
atic for power rails.</div>

<div><br></div><div>I now have a problem when I run gsch2pcb - the &#39;spl=
it&#39; ICs with the same refdes (i.e. power in subcircuit 1 (refdes SS1), =
signal in subcircuit 2 (refdes SS2)) are being placed twice on my PCB, with=
 names SS1/U1 and SS2/U1.</div>

<div><br></div><div>How can I force gsch2pcb to &#39;do the right thing&#39=
; here?=A0</div><div><br></div><div>Many thanks,</div><div>James.</div></di=
v><div class=3D"HOEnZb"><div class=3D"h5"><div class=3D"gmail_extra"><br><b=
r><div class=3D"gmail_quote">
On Sun, Oct 27, 2013 at 8:57 AM, Dave Curtis <span dir=3D"ltr">&lt;<a href=
=3D"mailto:davecurtis AT sonic DOT net" target=3D"_blank">davecurtis AT sonic DOT net</a>=
&gt;</span> wrote:<br>
<blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1p=
x #ccc solid;padding-left:1ex"><div>On 10/26/2013 12:08 PM, DJ Delorie wrot=
e:<br>
</div><div><div><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8e=
x;border-left:1px #ccc solid;padding-left:1ex">
Typically, you&#39;d have a separate symbol that had *only* the two power<b=
r>
pins, and the same refdes. =A0The netlister will merge those pins with<br>
the slotted pins when the schematic is exported.<br>
<br>
</blockquote></div></div>
That is exactly what I do. =A0It leads to cleaner schematics. =A0You can pu=
t the functional data flow on functional sheets, and infrastructure on infr=
astructure sheets, and neither clutters the other. =A0It makes schematics m=
uch more readable.<br>


<br>
In these days of mixed voltages all over the place, having implicit power c=
onnections just leads to confusion and bugs. =A0Better to show it all expli=
citly, IMCO (In my curmudgeonly opinion).<span><font color=3D"#888888"><br>


<br>
-dave<br>
<br>
</font></span></blockquote></div><br></div>
</div></div></blockquote></div><br></div>

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