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To: cygwin AT cygwin DOT com
Date: Sun, 12 Mar 2023 11:15:02 -0600
Message-Id: <announce.20230312111502.60214-1-Brian.Inglis@Shaw.ca>
Subject: [ANNOUNCEMENT] Updated: cpuid 20230306
From: Cygwin cpuid Maintainer via Cygwin-announce via Cygwin
 <cygwin AT cygwin DOT com>
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        Cygwin cpuid Maintainer <Brian DOT Inglis AT Shaw DOT ca>
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The following package has been upgraded in the Cygwin distribution:

* cpuid		20230306

Displays detailed information about the CPU(s) gathered from the
CPUID instruction, and also determines the exact model of CPU(s).

Whereas /proc/cpuinfo is like an abstract of the features important to
Linux in a system, cpuid is a standalone utility which writes a paper
expounding on every feature in each CPU's architecture and what it can
do, at about the one line per bit level.

It is updated and released frequently to stay current with Intel and
AMD information and supports other vendors' chips.

See the project home page for more information:

	http://etallen.com/cpuid.html

For information about changes since the previous Cygwin release,
see below or /usr/share/doc/cpuid/ChangeLog after installation.


Tue Mar  6 2023	20230306

* Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*), made
  the following (synth) changes: cpuid.c:

  - Updated (0,6),(3,7),8 Bay Trail with stepping name C0.
  - Added (0,6),(4,5),1 Haswell-ULT C0/D0 stepping.
  - Corrected (0,6),(4,6),1 Crystal Well to C0 stepping.
  - Updated (0,6),(4,7),1 Broadwell to include E0 stepping.
  - Added (0,6),(5,5),3 Skylake B1 (Xeon Scalable).
  - Added (0,6),(5,5),5 Skylake A0 (Xeon Scalable).
  - Added (0,6),(5,5),11 Cooper Lake A1 (Xeon Scalable).
  - Updated (0,6),(5,14),3 Skylake-H/S/E3, adding N0 & S0 steppings.
  - Added (0,6),(6,10),5 Ice Lake C0 (Xeon Scalable).
  - Added (0,6),(6,12),1 Ice Lake B0.
  - Updated (0,6),(8,6),4 Snow Ridge with stepping B0.
  - Updated (0,6),(8,6),5 Snow Ridge with stepping B1.
  - Added (0,6),(8,6),1 Lakefield B2/B3 stepping.
  - Corrected (0,6),(8,12),1 Tiger Lake stepping to B1.
  - Added (0,6),(8,12),2 Tiger Lake C0.
  - Added (0,6),(8,14),10 Coffee Lake D0.
  - Added (0,6),(8,14),13 Whiskey Lake-U V0 stepping.
  - Added (0,6),(8,15) Sapphire Rapids numerous steppings.
  - Updated (0,6),(9,12) Jasper Lake with stepping A1.
  - Differentiate (0,6),(8,10) Lakefield P-cores from Tremont E-cores,
    much as previously for Alder Lake & Raptor Lake.
  - In decode_uarch_intel, for known Hybrid chips (Alder Lake, Raptor
    Lake & Lakefield), only decode the uarch if it's one of the two
    known hybrid types. However, some (0,6),(9,7) Alder Lake's are
    non-hybrid (Golden Cove only), so also decode core type == 0x00
    there.
  - In the Intel Core era, uarch families are identified only by the
    initial uarch in the family. So the family names in {braces}, which
    also are uarch names, can be confusing. So, change (synth) and
    (uarch synth) for those families to explain the relationships
    between the subsequent uarch and the initial uarch, in the form of
    "shrink of", "optim of", and the unusual "backport of".
  - Added (4th Gen) to the (synth) description of (10,15),(1,*) AMD EPYC
    Genoa.
  - Updated (synth) for (10,15),(7,*) AMD Phoenix & Phoenix 2 CPUs to
    claim 4nm process.


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