Mail Archives: geda-user/2017/04/03/00:27:14
On Sun, 2 Apr 2017, al davis wrote:
> On Thu, 30 Mar 2017 19:20:40 +0200 (CEST)
> gedau AT igor2 DOT repo DOT hu wrote:
>> Do you have a file format spec you'd prefer? If it's about exporting
>> geometry from pcb-rnd, it's not very hard, I am sure we could get it done
>
> The structural subset of Verilog, using these guidelines for conveying
> layout info within the format.
>
> http://gnucap.org/dokuwiki/doku.php?id=gnucap:user:netlist_import_and_export
>
> It doesn't say how to express things like stackup and vias. Trace
> parameters like layers, thickness, width, and length are parameters to
> the "net". If a net is not all on the same layer, the complex net can
> be encapsulated, as introduced toward the end.
>
> I know this is not enough to catch every detail. This is the first
> one, and we need to experiment a little.
>
> The first step is to document specifically what the conversion needs to
> do, how one format is mapped to the other (and back again).
This looks like a netlist, I couldn't find a geometry description section.
From pcb-rnd we can export two things:
- geometry of the board: layers of traces, polygons, vias (the actual
2d geometry, and _not_ parasitics, capacitance, resistance, etc. values)
- the abstract netlist we worked from; but this won't have any info about
vias, traces, layers, materials - you just get back the input netlist that
you have exported from the schematics editor (tinycad, kicad, gschem,
ltspice, mentor graphics). In this setup all we do would be a netlist
syntax conversion. We could do this, but I think it wouldn't be a big step
forward in hooking up pcb edition with simulation.
Could you please show me an example on how your preferred format would
express the geometry?
And the good old question remains: what software would convert the pure
geometry to a netlist, extracting all the capacitance, resistance, etc.
values? Or is this the part the SoC project is for?
Regards,
Igor2
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