Mail Archives: geda-user/2017/01/28/15:54:23
Peter Clifton (petercjclifton AT googlemail DOT com) [via
geda-user AT delorie DOT com] schreef op za 28-01-2017 om 19:59 [+0000]:
>
>
> On 28 Jan 2017 19:00, "Richard Rasker (rasker AT linetec DOT nl) [via
> geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> wrote:
> I also tried approaching the issue from the other side,
> defining a loop antenna symbol in gschem with pins 1 and 2
> already connected through a net (pre-shorted, so to speak).
> However, PCB doesn't fall for this trick and bluntly keeps
> flagging this construct as a short, for reasons unknown.
>
>
> Was the net on the schematic page or inside the symbol? (I don't
> recall whether the netlist would spot the later).
It was inside the symbol, and yes, I also think that is why it isn't
acknowledged by the netlister.
> If you short the schematic, you might as well make both connection
> points on the antenna "1" though.... drc won't help you in either
> case.
It's even worse: since inadvertent shorts to ground (e.g. by moving vias
with certain layers switched off) are among the most commonly made
mistakes, using a 'pre-shorted' symbol is actually quite risky, also
because those antennas often have one net tied to ground.
Any accidental ground short in the antenna path has a high chance of
going unnoticed until the moment the actual PCB has been made and things
fail.
I think the best course of action is to simply leave the antenna
unconnected until last (which doesn't trigger any errors, even with
overlapping pads), and only hook it up after all the rest checks out OK.
> Anyway, as said it's not a big deal, mostly because designs
> usually don't have lots of antennas or other special elements
> made out of copper traces (e.g. inductors or heating areas).
> Still it would be nice if the functionality for this could be
> implemented some day.
>
> The other classic use (although slightly different) is implementing
> different net names for signals connecting a star ground. In this
> case, it isn't some rf or resistive component you instantiate, but a
> node point.
Ah, yes, I think I see the parallels here.
> In the antenna case, what you possibly want is copper shape
> definitions that are explicitly not followed for checking
> connectivity. (Might need to implement a keep away rule to avoid
> accidental shorts that could then go undetected).
>
> For the pcb resistor / inductors, I guess similar could work -
> although it is probably desirable to implement within some kind of
> "footprint" like construct in order to get the end connection points
> tested as a part of the netlist.
The above is indeed what I had in mind: a possibility to make some
copper traces/shapes invisible for the netlister, combined with one or
more normal pins or pads for proper netlist processing.
Then again, this introduces the problem of checking the 'no-net' copper
for shorts with other traces. In other words: how can be made certain
that any connections to this copper are made through the designated pins
exclusively? And that's probably just one of several tricky problems to
solve when treating not all copper in the same way...
Best regards,
Richard Rasker
Linetec
--
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e-mail: rasker AT linetec DOT nl
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