Mail Archives: geda-user/2017/01/21/12:28:36
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"John Luciani (jluciani AT gmail DOT com) [via geda-user AT delorie DOT com]"
<geda-user AT delorie DOT com> writes:
> For the thermal pads I typical reduce the coverage to
> between 50 - 70% (depending on the aperature dimensions).
Yep, good plan. You really want the reflow process to "suck the part
down" against the ground pad, or you'll have marginal results on the
connectivity of the signal pads.
A number of years ago, I built a footprint for a TI/Chipcon QFN-36 part
(the CC1111 RF system on chip), in which I meticulously followed their
recommendation to go even farther. They called for small spots of paste
on the exposed pad area between vias with mask over them. On these
parts, that pad is the *only* ground for the part, and since it's an RF
part getting the ground paths right is a big deal... so you *must* use
vias in the pad and handle them well or the part won't work very well.
This was a pain in the ass to figure out how to do in pcb. I wrote a
script that did the math and output a footprint with a lot of small
elements, some overlapping, to control exactly where copper, mask, and
paste get placed. Worked great, and we've shipped a lot of product
using this footprint and others like it that I've created in similar
fashion in the years since.=20
One of the lessons I learned from this was that I really prefer using
scripts to describe footprint geometry. I've never used a GUI to create
a footprint for PCB, and frankly just can't imagine wanting to...
In any case, if you want to see what I did, have a look at TI-QFN36.py
in the 'hw/altusmetrum' repo on git.gag.com, here's a direct link to the
file in question:
http://git.gag.com/?p=3Dhw/altusmetrum;a=3Dblob;f=3Dpackages/TI-QFN36.py
The script isn't "pretty", as it was hacked together over at least one
long night, but I suspect a real-life example could help some of you
trying to figure out how to do this stuff. This footprint has just
about all the craziness I've ever put in a QFN footprint (mask over
vias, partial exposure of the pad through the mask, small spots of paste
on the exposed pad, etc) all in one place...=20=20
Thanks to DJ, et al, for patiently answering questions for me on IRC way
back when as I first figured out how to do things like this in pcb...
All of the products shipped by Altus Metrum, LLC, to date have used a
makefile-driven gschem -> pcb workflow, and all of our designs are in
the hw/ tree on git.gag.com if anyone wants to learn more from studying
what we've done.=20
Bdale
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