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| From: | "John Luciani (jluciani AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
| Date: | Wed, 18 Jan 2017 19:09:38 -0500 |
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| Subject: | Re: [geda-user] QFN packages solder mask |
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--f403045ea286616962054667597a Content-Type: text/plain; charset=UTF-8 On Wed, Jan 18, 2017 at 2:40 PM, John Griessen (john AT ecosensory DOT com) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote: > On 01/18/2017 06:03 AM, John Luciani (jluciani AT gmail DOT com) [via > geda-user AT delorie DOT com] wrote: > >> What type of stencil openings are you using? >> > > I was thinking about .02mm more than the pad for the 0.5mm spacing pads > 0.3mm wide with a 0.2mm gap. > > but then I read where all the mfrs want those pad rows to be one open > rectangle. > > I have about 0.7mm openings for each pad that overlap, so a better way to > say it > is the no mask area extends 0.2mm beyong the pads. > I am talking about the solder stencil openings not soldermask. With these small parts it is difficult to maintain minimum soldermask widths. > > >> For the thermal pads I typical reduce the coverage to >> between 50 - 70% (depending on the aperature dimensions). >> The reduction is done using a layout similar to your footprint. >> The spacing between the paste areas provides the channels. >> >> I also reduce the coverage on the electrical pads. >> > > The small ones around the edge? > > Yes. I am talking about solder coverage not mask. For these small parts there is little if any mask left. > > I am going with a 9 pad grid in the center like the upper right of > > http://ecosensory.com/geda/qfn_lands_problem.png > > but with the mask opening like in the lower right. (No mask under edge, > no separation of center and edge row pads > but for lack of metal.) > > I'm planning on 4 center zone vias for heat and electrical contact. 5 > will only help stick it to the board. > > Now that I think of it, I should probably drastically reduce the paste and > metal of the non-via connected ones > to let bubbles out even better. It's not a high power app, just a > STM32F401CE. The go ahead and put the vias > into the footprint also. For now, I'll just place vias along with parts > and use the k key action command to resize pads. > > Any hints on success appreciated. > > I am suggesting a single center copper pad on the PCB and multiple pads cut in the solder stencil. All of the QFN application notes I have read recommend similar things. Checkout TI SLUA271A "QFN/SON Attachment" or NXP SOT1189-1 footprint recommendation. There are a lot more notes out there but these are the two I found quickly. The TI datasheets usually have detailed recommendations. For devices with vias I add them to the footprint. For each device with a power pad I make a stencil footprint with the same name but a sfp extension. When making the stencil you can have a script replace footprints with stencil footprints. John L > > -- > John Griessen -- building field gear for biologists > Ecosensory Austin TX ecosensory.com > -- http://www.wiblocks.com --f403045ea286616962054667597a Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable <div dir=3D"ltr"><div class=3D"gmail_extra"><div class=3D"gmail_quote">On W= ed, Jan 18, 2017 at 2:40 PM, John Griessen (<a href=3D"mailto:john AT ecosenso= ry.com">john AT ecosensory DOT com</a>) [via <a href=3D"mailto:geda-user AT delorie DOT c= om">geda-user AT delorie DOT com</a>] <span dir=3D"ltr"><<a href=3D"mailto:geda= -user AT delorie DOT com" target=3D"_blank">geda-user AT delorie DOT com</a>></span> w= rote:<br><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;borde= r-left:1px #ccc solid;padding-left:1ex"><span class=3D"">On 01/18/2017 06:0= 3 AM, John Luciani (<a href=3D"mailto:jluciani AT gmail DOT com" target=3D"_blank"= >jluciani AT gmail DOT com</a>) [via <a href=3D"mailto:geda-user AT delorie DOT com" targ= et=3D"_blank">geda-user AT delorie DOT com</a>] wrote:<br> <blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1p= x #ccc solid;padding-left:1ex"> What type of stencil openings are you using?<br> </blockquote> <br></span> I was thinking about .02mm more than the pad for the 0.5mm spacing pads 0.3= mm wide with a 0.2mm gap.<br> <br> but then I read where all the mfrs want those pad rows to be one open recta= ngle.<br> <br> I have about 0.7mm openings for each pad that overlap, so a better way to s= ay it<br> is the no mask area extends 0.2mm beyong the pads.<span class=3D""><br></sp= an></blockquote><div><br></div><div>I am talking about the solder stencil o= penings not soldermask. With these small parts it is difficult<br></div><di= v>to maintain minimum soldermask widths.<br></div><div>=C2=A0</div><blockqu= ote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc s= olid;padding-left:1ex"><span class=3D""> <br> <blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1p= x #ccc solid;padding-left:1ex"> <br> For the thermal pads I typical reduce the coverage to<br> between 50 - 70% (depending on the aperature dimensions).<br> The reduction is done using a layout similar to your footprint.<br> The spacing between the paste areas provides the channels.<br> <br> I also reduce the coverage on the electrical pads.<br> </blockquote> <br></span> The small ones around the edge?<br> <br></blockquote><div><br></div><div>Yes. I am talking about solder coverag= e not mask.<br></div><div>For these small parts there is little if any mask= left.<br></div><div><br>=C2=A0</div><blockquote class=3D"gmail_quote" styl= e=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> <br> I am going with a 9 pad grid in the center like the upper right of<br> <br> <a href=3D"http://ecosensory.com/geda/qfn_lands_problem.png" rel=3D"norefer= rer" target=3D"_blank">http://ecosensory.com/geda/qfn<wbr>_lands_problem.pn= g</a><br> <br> but with the mask opening like in the lower right.=C2=A0 (No mask under edg= e, no separation of center and edge row pads<br> but for lack of metal.)<br> <br> I'm planning on 4 center zone vias for heat and electrical contact.=C2= =A0 5 will only help stick it to the board.<br> <br> Now that I think of it, I should probably drastically reduce the paste and = metal of the non-via connected ones<br> to let bubbles out even better.=C2=A0 It's not a high power app, just a= STM32F401CE.=C2=A0 The go ahead and put the vias<br> into the footprint also.=C2=A0 For now, I'll just place vias along with= parts and use the k key action command to resize pads.<br> <br> Any hints on success appreciated.<div class=3D"HOEnZb"><div class=3D"h5"><b= r></div></div></blockquote><div><br><br></div><div>I am suggesting a single= center copper pad on the PCB and multiple pads cut in the solder stencil. = All of the QFN <br></div><div>application notes I have read recommend simil= ar things. Checkout TI SLUA271A "QFN/SON Attachment" or<br></div>= <div>NXP SOT1189-1 footprint recommendation. There are a lot more notes out= there but these are the two I found quickly. <br></div><div>The TI datashe= ets usually have detailed recommendations. <br><br></div><div>For devices w= ith vias I add them to the footprint. For each device with a power pad I ma= ke a stencil footprint<br></div><div>with the same name but a sfp extension= . When making the stencil you can have a script replace footprints<br></div= ><div>with stencil footprints.<br><br></div><div></div><div>John L<br></div= ><div><br></div><div><br><br><br>=C2=A0</div><blockquote class=3D"gmail_quo= te" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"= ><div class=3D"HOEnZb"><div class=3D"h5"> <br> -- <br> John Griessen -- building field gear for biologists<br> Ecosensory=C2=A0 Austin TX=C2=A0 <a href=3D"http://ecosensory.com" rel=3D"n= oreferrer" target=3D"_blank">ecosensory.com</a><br> </div></div></blockquote></div><br><br clear=3D"all"><br>-- <br><div class= =3D"gmail_signature" data-smartmail=3D"gmail_signature"><a href=3D"http://w= ww.wiblocks.com" target=3D"_blank">http://www.wiblocks.com</a> =C2=A0</div> </div></div> --f403045ea286616962054667597a--
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