www.delorie.com/archives/browse.cgi   search  
Mail Archives: geda-user/2016/01/26/14:58:55

X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f
X-Recipient: geda-user AT delorie DOT com
X-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=gmail.com; s=20120113;
h=mime-version:in-reply-to:references:date:message-id:subject:from:to
:content-type;
bh=kXpDeFNFsh9qlLoVlq91kNDSkxxVew475+LZ40mbY3s=;
b=bGbRsPfGJSmKGVRIzNXR36X7Ig7IF3ILxoSaQJ45NJ/h8xIu1ISi8CZChb6WrcyWVn
qto3d5bWwNXmomHVH5IPk6THe9J32gPWG/q+q4sPIR9RiqgdM/5axURzswntwsQMacJl
RgRanD88sP0wor4tNk9sYLR78VQLscHbfXZoJN8vcm0/dddJ70LUXM4XYuaQHdW4Cl3I
yQHUQTBSsVAtyrbqMG7gx3Y7mK/5B0AcO8fEieaPFmCVNVexNL+NsBTVff6SucE7udoo
lQYv/TnzEYN01ZZxhfVpOv4HoaYy8FTXTEbI9sSf31bGR+wEXSclPqSM/S7jGuNMCJEg
2RcQ==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20130820;
h=x-gm-message-state:mime-version:in-reply-to:references:date
:message-id:subject:from:to:content-type;
bh=kXpDeFNFsh9qlLoVlq91kNDSkxxVew475+LZ40mbY3s=;
b=bPtORxdmsdPPHMnsMB7e6tnimXH8YdeB9Fm7+fqKlRizGfi/1TPaWb/Z9X9NG3aPZD
tH5CJ041EWxxe1YAK7Zg1+nlHlMv20glCKc06iDXbqawGwfoGB1gkKp02BnDM6O6WKT1
xNLNl0n6M272WyFao+AOfo5FIst5nL/O798aP/qUKhM5WxW13M+YBz4hHtUfv8bMhrLh
pa/0fGaNqLwFAxUw1IrDRG5LYS87I7luYAm6fFpcsR5pMxyr2fZ6J09jT9iCd5WvOr2T
lcIpNG0cdoavnakAimQD57cbJRNm+bAKucrbwaxaV1VoYrbXphY5Rtr0MQkuuh6piaJn
pHSw==
X-Gm-Message-State: AG10YOQpO4fwBSC3xflNKKAhxVpH6EBvpul1SE1s/zoGzHXTbn7rH44xpdNermLMRqAx4xXt8Gg7BuMnEvh2sA==
MIME-Version: 1.0
X-Received: by 10.55.75.77 with SMTP id y74mr30210270qka.19.1453838325901;
Tue, 26 Jan 2016 11:58:45 -0800 (PST)
In-Reply-To: <201601261804.u0QI4KEQ009550@envy.delorie.com>
References: <alpine DOT DEB DOT 2 DOT 00 DOT 1601180756390 DOT 9035 AT igor2priv>
<alpine DOT DEB DOT 2 DOT 00 DOT 1601260416150 DOT 9035 AT igor2priv>
<56A751EC DOT 8030402 AT iae DOT nl>
<20160126124701 DOT 0d061912c7e078ced9d4e6cb AT gmail DOT com>
<CANEvwqgs3YFnt7m8mA1DN6X2KdWbyr4zpXCVH321vDo1f7CyxA AT mail DOT gmail DOT com>
<201601261804 DOT u0QI4KEQ009550 AT envy DOT delorie DOT com>
Date: Tue, 26 Jan 2016 14:58:45 -0500
Message-ID: <CANEvwqjrvyWVDVdaFdVNPKjeXBqgZTgzDNb8YStgcKQ4HARM2Q@mail.gmail.com>
Subject: Re: [geda-user] [pcb] poll: burried/blind vias vs. pcb and pcb-rnd
(How ?)
From: "Marvin Dickens (mpdickens AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To: geda-user <geda-user AT delorie DOT com>
Reply-To: geda-user AT delorie DOT com
Errors-To: nobody AT delorie DOT com
X-Mailing-List: geda-user AT delorie DOT com
X-Unsubscribes-To: listserv AT delorie DOT com

--001a114ab048f9f134052a421c48
Content-Type: text/plain; charset=UTF-8

I give up. With that said, for the record, I cannot afford to have a custom
ASIC
manufactured, but my client(s) can and do when an FPGA will not fulfill
design
requirements. Further, my point was all three types of property -medium to
large
FPGA's, ASICS's and BGA's require blind/buried vias. In addition, large
SOIC's,
are becoming cheap/popular for low production run designs benefit greatly
from
B/B vias - Places like Adafruit are beginning to pick up large SOIC designs
not to mention
they have published small FPGA designs for years. In fact, if your read the
blogs
at adafruit, the small FPGA's they have been using have "hit the wall" so
speak.
Even so, some of the adafuit designs already utilize B/B Vias.

So, there it is - Hobby/educational stuff using B/B via's...

Regards

Marvin

On Tue, Jan 26, 2016 at 1:04 PM, DJ Delorie <dj AT delorie DOT com> wrote:

>
> > In this day and age to say blind/buried vias are not needed is
> ridiculous.
> > The fact is ANY design that requires even one FPGA, custom ASIC or
> > medium to large BGA needs blind/buried vias.
> >
> > This is factual and is easy vetted.
>
> If you can afford a custom ASIC, you can afford a top-end EDA package,
> and a FAB that supports high-end features.  Frankly, PCB is not a
> high-end package and custom ASIC users are not our target audience.
>
> I can't afford any of that tech.  Heck, I can barely afford 4-layer
> boards with 6/6 rules.  There's a huge community of designers that
> can't (or won't) afford high tech features in their boards.
>
> So you can say "this is factual" but it's not.  It may be a
> requirement for a subset of our potential user base, but it's not
> ridiculous to assume that many people just aren't going to use them.
> Until we decide to support that tech, we're simply targetting the
> "many people" who don't need them.
>

--001a114ab048f9f134052a421c48
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr">I give up. With that said, for the record, I cannot afford=
 to have a custom ASIC=C2=A0<div>manufactured, but my client(s) can and do =
when an FPGA will not fulfill design</div><div>requirements. Further, my po=
int was all three types of property -medium to large</div><div>FPGA&#39;s, =
ASICS&#39;s and BGA&#39;s require blind/buried vias. In addition, large SOI=
C&#39;s,</div><div>are becoming cheap/popular for low production run design=
s benefit greatly from=C2=A0</div><div>B/B vias - Places like Adafruit are =
beginning to pick up large SOIC designs not to mention</div><div>they have =
published small FPGA designs for years. In fact, if your read the blogs</di=
v><div>at adafruit, the small FPGA&#39;s they have been using have &quot;hi=
t the wall&quot; so speak.</div><div>Even so, some of the adafuit designs a=
lready utilize B/B Vias.</div><div><br></div><div>So, there it is - Hobby/e=
ducational stuff using B/B via&#39;s...=C2=A0</div><div><br></div><div>Rega=
rds</div><div><br></div><div>Marvin</div></div><div class=3D"gmail_extra"><=
br><div class=3D"gmail_quote">On Tue, Jan 26, 2016 at 1:04 PM, DJ Delorie <=
span dir=3D"ltr">&lt;<a href=3D"mailto:dj AT delorie DOT com" target=3D"_blank">dj=
@delorie.com</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quote" sty=
le=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span =
class=3D""><br>
&gt; In this day and age to say blind/buried vias are not needed is ridicul=
ous.<br>
&gt; The fact is ANY design that requires even one FPGA, custom ASIC or<br>
&gt; medium to large BGA needs blind/buried vias.<br>
&gt;<br>
&gt; This is factual and is easy vetted.<br>
<br>
</span>If you can afford a custom ASIC, you can afford a top-end EDA packag=
e,<br>
and a FAB that supports high-end features.=C2=A0 Frankly, PCB is not a<br>
high-end package and custom ASIC users are not our target audience.<br>
<br>
I can&#39;t afford any of that tech.=C2=A0 Heck, I can barely afford 4-laye=
r<br>
boards with 6/6 rules.=C2=A0 There&#39;s a huge community of designers that=
<br>
can&#39;t (or won&#39;t) afford high tech features in their boards.<br>
<br>
So you can say &quot;this is factual&quot; but it&#39;s not.=C2=A0 It may b=
e a<br>
requirement for a subset of our potential user base, but it&#39;s not<br>
ridiculous to assume that many people just aren&#39;t going to use them.<br=
>
Until we decide to support that tech, we&#39;re simply targetting the<br>
&quot;many people&quot; who don&#39;t need them.<br>
</blockquote></div><br></div>

--001a114ab048f9f134052a421c48--

- Raw text -


  webmaster     delorie software   privacy  
  Copyright © 2019   by DJ Delorie     Updated Jul 2019