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Mail Archives: geda-user/2016/01/06/05:49:23

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From: geda AT psjt DOT org (Stephan =?utf-8?Q?B=C3=B6ttcher?=)
To: <geda-user AT delorie DOT com>
Subject: Re: [geda-user] A fileformat library
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Date: Wed, 06 Jan 2016 11:48:58 +0100
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(Britton Kerin's message of "Tue, 5 Jan 2016 14:52:37 -0900")
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"Britton Kerin (britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com]"
<geda-user AT delorie DOT com> writes:

> The big potential down-side to *extending* via (not just supporting)
>  YAML/JSON/SQL, relative to extending the existing format is that tools
> that do partial parse have no chance to continue working unmodified.  This
> sounds worse than it is though.

Those "tools that do partial parse" are awk and sed, and small scripts,
typed day to day fresh on the commandline, or embedded in Makefiles.
Those will adapt to whatever extensions are added to the file
format.  But they must not become non-awk-parsable.

Those "tools that do partial parse" are required to solve problems, or
provide features, that the primary tools do not provide, yet, but which
need solutions now.

E.g., rigid-flex boards.  One of those is right now driving around on
Mars, designed with gaf and pcb.  Other boards in the same box have
complex shapes, with lots of Arcs.  Those where designed with gnumeric,
which yielded a pcb file fragments that were cut&paste into the layout
file.  Like this one:
http://www.ieap.uni-kiel.de/et/people/stephan/msl/eda/RADE/RADE-silk.png

This kind of accessibility to the file format is what keeps me using gaf
and pcb.  The tools will never do all what I need natively, when I need
it.


An nice addition/alternative to accessible file formats is discoverable
scripting in the layout tool.

I once used that with Silicon Explorer for an ASIC.  The layout tool had
a window that logs every modification of the layout in form of script
commands.

I cut&paste those logs into a big script that did the complete ASIC
from scratch.  When I changed the Verilog source and typed 'make all',
the whole design flow would run automatically.  Simulation, sythesis,
simulation, layout, place and route, drc, lvs, simulation.  This worked
because there was not much that needed to be drawn by hand, and because
the scriping/syntax was very discoverable.

Does pcb scripting support drawing a line between to points?  There may
be a lot that can be done with scripts in PCB.  But it is certainly not
discoverable, and from what I read from the manual, once I found it,
it is not complete.  You cannot :ExecuteFile() a script into an empty
layout and get a finshed board, can you?   If you could, that script
would be a file format for layouts.  Next, I'd ask for an export hid to
write such scripts.

If the current file format is extended by adding layer fields to all
objects, those object stanzas become script commands:

 Line["signal2" 119.6929mm 101.0041mm 4757.60mil 102.9959mm 0.2500mm 0.5000mm "clearline"]

Add layer fields to Via to support blind/burried vias.

The layer fields in the objects inside an Element support: text on silk,
boards with more than two outer layers, ...

This might need to be complemeted with another syntax/indirection level
for specifying layers.

  "flextop", "flextop:silk", "flextop:mask", "flextop:paste", "flextop:outline"

The data model becomes more othogonal, no restrictions what can be drawn where.

Step 1. teach PCB to read this format within scripts.  Throw Errors when
something is drawn where the current data model does not allow.

Step 1b: allow this format in layout files.

Step 2. teach PCB to write this format.

Steps 3...: change the internal data model to support more and more of cases. 

-- 
Stephan

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