Mail Archives: geda-user/2015/02/09/10:21:16
On Feb 9, 2015, at 2:08 AM, Chris Smith <space DOT dandy AT icloud DOT com> wrote:
>
>> On 8 Feb 2015, at 20:47, John Griessen <john AT ecosensory DOT com> wrote:
>>
>> Sounds like replacing the scheme with lua could be a bit more than one mythical-man-month of work
>> if not done by just one person, so something realistic to consider.
>> There's still the C language layer. The nitty gritty parts. That needs some architecture
>> description written before charging ahead with replacing scheme, since much of that deserves redoing to get hierarchic
>> schematics and netlists working well for anything including embedded verilog logic circuit definitions.
Paul Tan has been doing hierarchical Verilog with geda-gaf for years. See http://archives.seul.org/geda/user/Jan-2009/msg00056.html. Stuart Brorson’s spice-sdb has hierarchy support, and chips I designed using it will fly on the ASTRO-H space mission. My https://github.com/noqsi/gnet-spice-noqsi makes hierarchical SPICE a bit more convenient: the only part not automated is keeping track of which source files belong to which subcircuit, and which subcircuits go in the design.
>
> In terms of hierarchical schematics, etc. what do you think is missing?
Specs for netlists to export from gnetlist to support printed circuit layout. Apparently, some layout tools can handle hierarchy. For Verilog and SPICE we know what the files need to look like, so we can do the export. My ASIC layout contractor takes hierarchical SPICE as input for layout. But for printed circuits, I don’t know what to export.
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
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