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From:	Joshua Lansford <joshua DOT lansford AT laserlinc DOT com>
Date:	Sat, 31 Aug 2013 15:27:30 -0400
Message-ID:	<CAGRhJMag+hNGutkiG6Mgr9+vxaSynkNEajR0HE2gs8GeZM0o0Q@mail.gmail.com>
Subject:	[geda-user] VE
To:	geda-user AT delorie DOT com
Reply-To:	geda-user AT delorie DOT com

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Hey guys,
  Sorry if this is too off topic.  Am wanting to share a pet project I did
a while back.  Kind of been emboldened to share it by others sharing. :-P
  I have been seeing the industry slowly moving from Verilog and VHDL to
higher-level languages for FPGA firmware and ASIC design.  Xilinx is
pushing a C to HDL converter but it definitely isn't free.
  I wrote a proof of concept higher level language compiler which compiles
down to synthesizable Verilog which can also be simulated by gEDA icarus.
 It is open source and hosted here:
https://github.com/JEdward7777/VerilogExpress

Here is an example of the code.  Blocks of code which start with [ and ]
are executed simultaneously while blocks which start and end with { } are
executed sequentially.  There currently are two var types.  Pipes and
Registers.  Pipes block on read or write until the other-side has a read or
write.
Inputs and outputs to a module are Pipes which include the data bits and
read and write control signals.

module gcd[
  input aIn;
  input bIn;
  output oOut;

  while( 1 ){
    reg aReg = 0;
    reg bReg = 0;
    [ aReg = aIn; bReg = bIn; ]

    while( bReg != 0 ){
      if( aReg < bReg )[
        aReg = bReg;
        bReg = aReg;
      ]else
        aReg = aReg - bReg;
    }

    oOut = aReg;
  }
]

The project is not currently moving, but thought perhaps folks might find
it interesting.  Currently all the vars are stuck at 32 bits, but Verilog
synthesizers generally get rid of unused bits anyway.
An argument for this type of language is that FPGAs are getting bigger and
bigger but people aren't getting smarter and smarter.  As writing in
assembly is often not as usefull now days as c or some other higher level
laungauge even though it isn't as efficient, it keeps projects rolling
because the simplifications allows greater project complexities. The same
seems to be true with hardware development, but I am not aware of any other
open source project working in this direction.
~Joshua

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<div dir=3D"ltr">Hey guys,<div>=A0 Sorry if this is too off topic. =A0Am wa=
nting to share a pet project I did a while back. =A0Kind of been emboldened=
 to share it by others sharing. :-P</div><div>=A0 I have been seeing the in=
dustry slowly moving from Verilog and VHDL to higher-level languages for FP=
GA firmware and ASIC design. =A0Xilinx is pushing a C to HDL converter but =
it definitely isn&#39;t free.</div>

<div>=A0 I wrote a proof of concept higher level language compiler which co=
mpiles down to synthesizable Verilog which can also be simulated by gEDA ic=
arus. =A0It is open source and hosted here:=A0</div><div><a href=3D"https:/=
/github.com/JEdward7777/VerilogExpress">https://github.com/JEdward7777/Veri=
logExpress</a><br>

<br></div><div>Here is an example of the code. =A0Blocks of code which star=
t with [ and ] are executed simultaneously while blocks which start and end=
 with { } are executed sequentially. =A0There currently are two var types. =
=A0Pipes and Registers. =A0Pipes block on read or write until the other-sid=
e has a read or write.</div>

<div>Inputs and outputs to a module are Pipes which include the data bits a=
nd read and write control signals.</div><div><br></div><div><div>module gcd=
[</div><div>=A0 input aIn;</div><div>=A0 input bIn;</div><div>=A0 output oO=
ut;</div>

<div><br></div><div>=A0 while( 1 ){</div><div>=A0 =A0 reg aReg =3D 0;</div>=
<div>=A0 =A0 reg bReg =3D 0;</div><div>=A0 =A0 [ aReg =3D aIn; bReg =3D bIn=
; ]</div><div><br></div><div>=A0 =A0 while( bReg !=3D 0 ){</div><div>=A0 =
=A0 =A0 if( aReg &lt; bReg )[ =A0</div>

<div>=A0 =A0 =A0 =A0 aReg =3D bReg;</div><div>=A0 =A0 =A0 =A0 bReg =3D aReg=
;</div><div>=A0 =A0 =A0 ]else</div><div>=A0 =A0 =A0 =A0 aReg =3D aReg - bRe=
g;</div><div>=A0 =A0 }</div><div><br></div><div>=A0 =A0 oOut =3D aReg;</div=
><div>=A0 }</div><div>]</div></div><div><br>

</div><div>The project is not currently moving, but thought perhaps folks m=
ight find it interesting. =A0Currently all the vars are stuck at 32 bits, b=
ut Verilog synthesizers generally get rid of unused bits anyway.</div><div>

An argument for this type of language is that FPGAs are getting bigger and =
bigger but people aren&#39;t getting smarter and smarter. =A0As writing in =
assembly is often not as usefull now days as c or some other higher level l=
aungauge even though it isn&#39;t as efficient, it keeps projects rolling b=
ecause the simplifications allows greater project complexities. The same se=
ems to be true with hardware development, but I am not aware of any other o=
pen source project working in this direction.</div>

<div>~Joshua</div></div>

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