Mail Archives: geda-user/2013/08/27/05:13:43
> Myken, thanks for the effort, I will use this when I have time to do
> so. It looks great so far. Just a reminder, spell check doesn't catch
> grammar errors which can become quite important for translations. Let
> us know when you think your tutorial is ready for prime time!
Thanks Jan, English it's my first/native language (although my ego tells
me I'm pretty good at it ;-) I know I'm not) so any help is GREATLY and
VERY appreciated.
> I've also found on several separate gEDA installs gafrc doesn't work for
> homemade symbols, I've always had to add my own stuff directly to the
> main symbol libraries in order for my existing schematics to display
> properly. Which leads me to think gafrc doesn't work at all. Perhaps
> you could explore this in your tutorial, maybe it's a bug that's been
> around for a long time?
I have not found any reference to that kind of problems with gafrc.
Maybe you can try making a file "whatever.sch" in the same directory as
your gafrc and them open "whatever.sch". It can be that your
installation uses a default directory when you open gschem from a menu.
If the problem persist I would advice you to make a bug report.
>
> On 08/26/2013 10:05 AM, myken wrote:
>>> Fine -- indeed I was wondering in the last weeks what you was doing with
>>> gEDA and VHDL -- my initial guess was that you tried to generate
>>> schematics from VHDL code.
>> You are absolutely right. That was/is my primary trigger. But first I
>> had to figure out how the gschem to VHDL path works. So why not let
>> everybody profit from my work ;-)
>> Unfortunately I got stonewalled by the way gschem/gnetlist (VHDL
>> backend) handles buses. I haven't solved that one.
>>> Maybe you should start your tutorial indeed with a short remark what you
>>> intend -- starting with statements about bugs is very negative in
>> Good point. I'll add an introduction.
>>> general. And from my knowledge the way schematic -> VHDL is not very
>>> common, VHDL was invented to allow textual input, maybe generate
>>> schematic output for verifying the result. Of course the direction
>>> schematic VHDL may be justified, i.e. for very special digital
>>> circuits.
>> Oh really? I usually use the schematics to define the architecture or
>> communicate about the architecture and fill in the working block
>> later. But I guess that makes me special :-)
>>> I had only a short look at your page -- is my impression wrong that your
>>> general used font is smaller than the users default?
>> It should not be. I'll test it on an other machine later tonight.
>>
>>
>
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