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Date:	Mon, 19 Aug 2013 11:03:55 +0200
From:	myken <myken AT iae DOT nl>
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To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] Include VHDL code in sym file?
References:	<520F96F1 DOT 2090304 AT iae DOT nl> <F4EF3868-82D8-4F4F-B060-A5B0498D1EC9 AT noqsi DOT com>
In-Reply-To:	<F4EF3868-82D8-4F4F-B060-A5B0498D1EC9@noqsi.com>
Reply-To:	geda-user AT delorie DOT com

Thanks, I'll look into that.

On 17/08/13 18:10, John Doty wrote:
> On Aug 17, 2013, at 9:29 AM, myken wrote:
>
>> Hello all,
>>
>> Is it possible to include VHDL code in the sym file or attach it through an external file?
> Sure. Just stick it in an attribute.
>
>> I like to use gschem to make a top level design and include some VHDL blocks. After that I will generate the VHDL code through gnetlist. It would be nice if I could include some VHDL code which will also be include in the code generated by gnetlist.
> I don't know how the vhdl back end for gnetlist works. However, my experimental SPICE back end at https://github.com/noqsi/gnet-spice-noqsi processes symbol attributes (spice-prototype and file) as well as toplevel attributes (spice-prolog and spice-epilog) to create arbitrary SPICE code output. It processes these through a simple macro expander, so they can refer to other attributes and net/pin connections. This might be an approach you could use for VHDL as well.
>
> John Doty              Noqsi Aerospace, Ltd.
> http://www.noqsi.com/
> jpd AT noqsi DOT com
>
>
>
>

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