Mail Archives: geda-user/2013/06/19/13:05:03
On Jun 18, 2013, at 3:46 PM, Hannu Vuolasaho wrote:
> So what is easiest way to simulate subcircuit without breaking the schematics for PCB?
>
> And more of a developing philosophical question is why there are two incompatible hierarchy mechanics?
There are a number of conflicts between the nature of a printed circuit netlist and a simulation netlist. Most printed circuit flows use flat netlists, but simulation netlists are hierarchical. Refdes prefixes often conflict between printed circuit convention (transistors use Q) versus SPICE (transistors use Q, J, M, or X, depending on type). Printed circuit design revolves around physical packages, but the elements of a simulation don't necessarily correspond to those packages (what package does a SPICE "K" device come in?). Connections to networks are generally by pin number in printed circuit netlists, but positional within the device instance in SPICE netlists. In simulation, it is sometimes desirable to replace a complex block with a simpler model (voltage source for a power supply), or draw a schematic representing a packaged device. The depth of hierarchy where one stops the netlister thus varies in simulation. but in a printed circuit flow one generally stops at the physical package level.
The design of gnetlist is oriented more toward printed circuit flows. By default, it automatically flattens hierarchy. But for SPICE, you don't want that, and you need to provide subcircuit definitions and instances explicitly in the netlist. It is thus difficult to use the same hierarchy mechanics in both cases. For connection order, symbols have the pinseq= attribute on pins. That works fine for simple components, but slotted components use pinseq= to identify pin function in a way that conflicts with SPICE connection ordering.
But difficult does not mean impossible. You can turn gnetlist's hierarchy traversal off. That allows the back end to see the symbols representing the hierarchical connections. It can then translate them to subcircuit instances or declarations. For slotted components, a back end can identify connections by pinnumber= rather than pinseq=. The symbol creator can specify the simulation refdes prefix in an attribute.
I have a gnetlist back end at https://github.com/noqsi/gnet-spice-noqsi implementing this approach. I now use it for all of my SPICE work. It has no documentation other than a README, unfortunately. I have more work to do...
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
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