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Date:	Tue, 22 Dec 2015 22:53:29 +0100
From:	"Peter Stuge (peter AT stuge DOT se) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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Subject:	Re: [geda-user] Verilog as netlist format
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Stephan Böttcher wrote:
> I thought about using Verilog as netlist format for PCBs.  How would I
> convert those to pcb netlists, with some graphical drawings added in the
> mix?

I would look at reusing/extending the Verilog code in Yosys.


//Peter

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