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Date:	Wed, 9 Sep 2015 11:45:50 +0200 (CEST)
From:	Roland Lutz <rlutz AT hedmen DOT org>
To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] New experimental netlist features
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On Tue, 8 Sep 2015, DJ Delorie wrote:
>> I'm not a fan of notations where the first and last included element 
>> are mentioned; but I realize some users might want to use such a 
>> format, so I allowed typing "0..7" instead of "0:8".
>
> Aren't there standards for this already?  I'm thinking of verilog...

I wasn't aware of Verilog; my syntax is inspired by Pascal ("0 to 7") and 
Python ("0:8").

On Tue, 8 Sep 2015, DJ Delorie wrote:
> I looked up the verilog and its [msb:lsb]
>
> so D[6:4] would be three signals (D6,D5,D4), and D[4:6] would be the
> same three signals in the other order.

That's unfortunate.  So there are two conflicting interpretations for a 
common notation...

Do you have any suggestion for a less ambiguous syntax?

Roland

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