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| 26 Aug 2015 12:25:50 -0700 (PDT) | |
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| Date: | Wed, 26 Aug 2015 15:25:50 -0400 |
| Message-ID: | <CAM2RGhTqdvbwNrd78EQMU=+BTG=EZC1CB+E9ddnco8Mm0CemQQ@mail.gmail.com> |
| Subject: | Re: [geda-user] pcb file format |
| From: | "Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
| To: | geda-user AT delorie DOT com |
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On Wed, Aug 26, 2015 at 2:03 PM, DJ Delorie <dj AT delorie DOT com> wrote: > >> Exactly. PCB currently does this only it does not have all the >> information in a unified structure. > > It's in 'extern PCBType *PCB;' so while the structure may be a little > obtuse, it's certainly unified. Sorry mis spoke/typed. Look you all know what my view is on this and most of you share it. >> It does iterate through the list of connected items and build a >> netlist but things like design rules are apparently processed in a >> messier way. > > Because the concept of "connected" in pcb becomes a geometry problem, > not a logic problem. DRC is messy because it's a messy problem to > solve, with many solutions, and the one originally chosen wasn't > neccessarily the one we might have chosen today. > > (btw: drc is handled by running the netlist code multiple times, so > that "but" doesn't work that way either - it's the *same* code ;) Ok -- Home http://evanfoss.googlepages.com/ Work http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/
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