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Date:	Thu, 9 Jul 2015 22:22:13 +0000
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Subject:	Re: [geda-user] Back annotation
From:	"Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On 7/9/15, DJ Delorie <dj AT delorie DOT com> wrote:
>
>> #3 is certainly growing on me. I find myself dealing with multiple
>> layout contractors, and one of them wants footprint names like
>> "BGA484C100P22X22_2300X2300X260". I don't think those belong in the
>> schematics, and the others are happy with "BGA484". So, it's a
>> flow-dependent mapping.
>
> That idea was a side-effect of my "component database" blue-sky.  We really
> want *three* main tools:
>
> * schematic capture (gschem)
> * mapping to a backend (netlister + component_db + project_ruleset)
> * backend (pcb/sim/etc)
>
> The mapping would map symbolic information (pins A,B,Y, value, etc) to
> physical information (package-specific pinouts, simulation models,
> etc) based on whatever relevent local rules apply.  Most of this info
> is what's back-annotated anyway, but the backend can provide its
> as-built data to the netlister on the fly, to merge with new schematic
> info.
>
> It's also a solution to the transistor problem, because the
> information that's moved out of the schematic is the same information
> that causes the problem in the first place.
>
> And by swapping the db/rules you get to target different backends with
> the same schematics.
>
> One of the "backends" could be an annotated as-built schematic set too :-)
>
> /me wonders how this will work with heriarchical "symbols" feeding
> ruleset attributes to subcircuits...

How do you prompt the user for the information in a way that is not
painfully breaking their flow.

Perhaps if you back-annotate while using subcircuits it should present
you with two options side by side?

-- 
Home
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Work
http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/

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