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Subject:	Re: [geda-user] Back annotation
From:	John Doty <jpd AT noqsi DOT com>
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Date:	Thu, 9 Jul 2015 11:53:27 -0600
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On Jul 9, 2015, at 11:16 AM, Britton Kerin (britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:

>> For my ASIC designs, the parameter extracted netlists are about 200x the size of the netlists generated from the schematics. Printed circuit designs are generally flatter, but back-annotation into even a simple circuit still looks impractical to me. There’s really no utility to it anyway: the netlist is what you need as input for your verification process.
> 
> Since you don't do layout work, how would you know?

Because I’ve done the verification.

> 
> Britton
> 
> 

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com

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