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Date:	Thu, 22 Aug 2013 10:11:39 +0200
From:	myken <myken AT iae DOT nl>
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To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] How to contribute standard symbol files?
References:	<521481EE DOT 2010103 AT iae DOT nl> <87zjsa7uh5 DOT fsf AT harrington DOT peter-b DOT co DOT uk>
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Reply-To:	geda-user AT delorie DOT com

> Hi Robert,
>
> If possible, it would be good if you could fix the generation of the
> VHDL symbols...
>
> Peter
Yes, I thought of that. Unfortunately it would mean a rather big change 
in the current script. The current script doesn't do much, it changes 
device=and to device=and[2..9], that's it. But to make the vhdl library 
usable more changes are needed.
Oh well maybe I'll start working on it.
Is there a verilog library maintainer?

Thanks, Robert

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