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| Date: | Wed, 24 Oct 2012 18:26:25 +0200 |
| From: | Jan Kasprzak <kas AT fi DOT muni DOT cz> |
| To: | geda-user AT delorie DOT com |
| Subject: | Re: [geda-user] Trace width - best practices? |
| Message-ID: | <20121024162625.GW32696@fi.muni.cz> |
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Bob Paddock wrote:
: On Tue, Oct 23, 2012 at 3:24 PM, Jan Kasprzak <kas AT fi DOT muni DOT cz> wrote:
:
: > Note that I don't want the whole net to be made from wider traces,
: > only connections between some of the pins of the same net should be made wider.
:
: These are better known as Fuses, and are generally a bad idea.
: Not saying it is not very common, just consider the Fuse aspect.
:-) Interesting. But burning the trace in PCB can still be better
than burning the components.
: > - this decoupling capacitor should be placed as close to this chip as possible
: >
: > or
: >
: > - these four connections together form a current loop, and the loop as a whole
: > should be made as short as possible
:
: It would be great to mark segments of the same net with attributes in
: both PCB and the schematic.
The problem (both with gschem nets and pcb rats' nests) is that
the segments of the net don't match the actual routes. I for example
can have net (rat's nest) A-B-C displayed as one segment between A and B,
and one segment between B and C. However, I may need the high-current trace
only between A and C. So it might make sense to draw a thick trace between
A and C (and place A and C as close to each other as possible), and
then draw a thin branch from any point of that trace to the pin B.
So I think net (or net segment) attributes are not the best
place for storing such information. This information is essesntially
pin-to-pin based, not net segment based.
: What I have below here was
: written on a different list to a different question but the
: information is relevant to yours:
Interesting, thanks!
-Yenya
--
| Jan "Yenya" Kasprzak <kas at {fi.muni.cz - work | yenya.net - private}> |
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| http://www.fi.muni.cz/~kas/ Journal: http://www.fi.muni.cz/~kas/blog/ |
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