8.19.1 Assembler options
The MIPS configurations of GNU
as support these
- This option sets the largest size of an object that can be referenced
implicitly with the
gp register. It is only accepted for targets
that use ECOFF format. The default value is 8.
- Any MIPS configuration of
as can select big-endian or
little-endian output at run time (unlike the other GNU development
tools, which must be configured for one or the other). Use `-EB'
to select big-endian output, and `-EL' for little-endian.
- Generate code for a particular MIPS Instruction Set Architecture level.
`-mips1' corresponds to the R2000 and R3000 processors,
`-mips2' to the R6000 processor, `-mips3' to the
R4000 processor, and `-mips4' to the R8000 and
R10000 processors. `-mips5', `-mips32', and
`-mips64' correspond to generic MIPS V, MIPS32, and
MIPS64 ISA processors, respectively. You can also switch
instruction sets during the assembly; see Directives to override the ISA level.
- Some macros have different expansions for 32-bit and 64-bit registers.
The register sizes are normally inferred from the ISA and ABI, but these
flags force a certain group of registers to be treated as 32 bits wide at
all times. `-mgp32' controls the size of general-purpose registers
and `-mfp32' controls the size of floating-point registers.
On some MIPS variants there is a 32-bit mode flag; when this flag is
set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
save the 32-bit registers on a context switch, so it is essential never
to use the 64-bit registers.
- Assume that 64-bit general purpose registers are available. This is
provided in the interests of symmetry with -gp32.
- Generate code for the MIPS 16 processor. This is equivalent to putting
`.set mips16' at the start of the assembly file. `-no-mips16'
turns off this option.
- Generate code for the MIPS-3D Application Specific Extension.
This tells the assembler to accept MIPS-3D instructions.
`-no-mips3d' turns off this option.
- Generate code for the MDMX Application Specific Extension.
This tells the assembler to accept MDMX instructions.
`-no-mdmx' turns off this option.
- Cause nops to be inserted if the read of the destination register
of an mfhi or mflo instruction occurs in the following two instructions.
- Generate code for the LSI R4010 chip. This tells the assembler to
accept the R4010 specific instructions (`addciu', `ffc',
etc.), and to not schedule `nop' instructions around accesses to
the `HI' and `LO' registers. `-no-m4010' turns off this
- Generate code for the MIPS R4650 chip. This tells the assembler to accept
the `mad' and `madu' instruction, and to not schedule `nop'
instructions around accesses to the `HI' and `LO' registers.
`-no-m4650' turns off this option.
- For each option `-mnnnn', generate code for the MIPS
RNNNN chip. This tells the assembler to accept instructions
specific to that chip, and to schedule for that chip's hazards.
- Generate code for a particular MIPS cpu. It is exactly equivalent to
`-mcpu', except that there are more value of cpu
understood. Valid cpu value are:
- Schedule and tune for a particular MIPS cpu. Valid cpu values are
identical to `-march=cpu'.
- Generate code and schedule for a particular MIPS cpu. This is exactly
equivalent to `-march=cpu' and `-mtune=cpu'. Valid
cpu values are identical to `-march=cpu'.
Use of this option is discouraged.
- This option is ignored. It is accepted for command-line compatibility with
other assemblers, which use it to turn off C style preprocessing. With
as, there is no need for `-nocpp', because the
GNU assembler itself never runs the C preprocessor.
--no-construct-floats option disables the construction of
double width floating point constants by loading the two halves of the
value into the two single width floating point registers that make up
the double width register. This feature is useful if the processor
support the FR bit in its status register, and this bit is known (by
the programmer) to be set. This bit prevents the aliasing of the double
width register by the single width registers.
--construct-floats is selected, allowing construction
of these floating point constants.
as automatically macro expands certain division and
multiplication instructions to check for overflow and division by zero. This
as to generate code to take a trap exception
rather than a break exception when an error is detected. The trap instructions
are only supported at Instruction Set Architecture level 2 and higher.
- Generate code to take a break exception rather than a trap exception when an
error is detected. This is the default.
- When this option is used,
as will issue a warning every
time it generates a nop instruction from a macro.