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as for MIPS architectures supports several
different MIPS processors, and MIPS ISA levels I through V, MIPS32,
and MIPS64. For information about the MIPS instruction set, see
MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall).
For an overview of MIPS assembly conventions, see "Appendix D:
Assembly Language Programming" in the same work.
8.19.1 Assembler options 8.19.2 MIPS ECOFF object code ECOFF object code 8.19.3 Directives for debugging information 8.19.4 Directives to override the ISA level 8.19.5 Directives for extending MIPS 16 bit instructions 8.19.6 Directive to mark data as an instruction 8.19.7 Directives to save and restore options 8.19.8 Directives to control generation of MIPS ASE instructions
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