Format of Via Technologies' VT82C580VPX CPU-PCI bridge configuration:
Offset	Size	Description	)
 00h 64 BYTEs	header (see #00878)
		(vendor ID 1106h, device ID 0585h)
 40h 16 BYTEs	unused
 50h	BYTE	cache control 1
 51h	BYTE	cache control 2
 52h	BYTE	non-cacheable control
 53h	BYTE	system performance control
 54h	BYTE	non-cacheable region 1 (high)
 55h	BYTE	non-cacheable region 1 (low)
 56h	BYTE	non-cacheable region 2 (high)
 57h	BYTE	non-cacheable region 2 (low)
 58h	BYTE	DRAM configuration 1
 59h	BYTE	DRAM configuration 2
 5Ah  6	BYTEs	DRAM row N ending address (N=0-5)
 60h	BYTE	DRAM type
 61h	BYTE	shadow RAM control 1
 62h	BYTE	shadow RAM control 2
 63h	BYTE	shadow RAM control 3
 64h	BYTE	DRAM reference timing
 65h	BYTE	DRAM timing control 1 (see #00996)
 66h	BYTE	DRAM timing control 2 (see #00997)
 67h	BYTE	32-bit DRAM width (see #00998)
 68h	BYTE
 69h	BYTE	reserved ("do not program")
 6Ah	BYTE	refresh counter
 6Bh	BYTE	refresh control
 6Ch	BYTE	SDRAM control
 6Dh	BYTE	DRAM control drive strength
 6Eh  2 BYTEs	reserved
 70h	BYTE	PCI buffer control
 71h	BYTE	CPU-to-PCI flow control 1
 72h	BYTE	CPU-to-PCI flow control 2
 73h	BYTE	PCI master control 1
 74h	BYTE	PCI master control 2
 75h	BYTE	PCI arbitration 1
 76h	BYTE	PCI arbitration 2
 77h	BYTE	reserved for chip test
 78h 136 BYTEs	reserved
!!!via\580vpx.pdf
SeeAlso: #00817