Format of PCI Configuration data for Intel 82434LX/NX Cache/DRAM Controller:
Offset	Size	Description	)
 00h 64 BYTEs	header (see #00878)
		(vendor ID 8086h, device ID 04A3h)
		(revision numbers: 01h/03h are 82434LX, 1xh are 82434NX)
		(command register only supports bits 8,6,2,1,0)
 40h 16 BYTEs	unused (hard-wired to 00h)
 44h	BYTE	??? (AMI BIOS writes 00h)
 45h	BYTE	??? (AMI BIOS writes 00h)
 50h	BYTE	Host CPU Selection (see #01056)
 51h	BYTE	deturbo frequency control register
		when deturbo mode is selected (see PORT 0CF9h), the chipset
		  places a hold on the memory bus for a fraction of the
		  time inversely proportional to the value in this register
		  by comparing it against a free-running 8-bit counter counting
		  at 1/8 the CPU clock speed
		  (i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.)
		  (only bits 7-6 writable, bits 5-0 hardwired to 0)
 52h	BYTE	Secondary Cache Control (see #01057)
 53h	BYTE	Host Read/Write Buffer Control (see #01058)
 54h	BYTE	PCI Read/Write Buffer Control
		bits 7-3: reserved
		bit 2: LBXs connected to TRDY#
		bit 1: enable PCI burst writes
		bit 0: enable PCI-to-memory posted writes
 55h  2 BYTEs	reserved
 57h	BYTE	DRAM Control (see #01059)
 58h	BYTE	DRAM Timing (see also #01117)
		bits 7-2: reserved
		bit 1: (NX only) RAS# Wait State
		bit 0: CAS# Wait State (one extra wait state before CAS#
			  within burst cycle)
 59h  7	BYTEs	Programmable Attribute Map registers 0-6 (see #01118)
 60h  8	BYTEs	DRAM Row Boundary registers 0-7
		(chip revisions numbered < 10h [LX] only support six rows of
		each register N indicates the amount of cumulative amount of
		  memory in SIMM banks 0-N, in multiples of 1M; offset 67h
		  (65h on 82434LX's) contains the total amount of memory
		  installed in the system; on the 82434NX, two additional
		  bits are concatenated to each row boundary from the DRAM Row
		  Boundary Extension registers to allow up to 1024M of memory
		  to be specified (though only 512M are supported)
 68h  4 BYTEs	(NX only) DRAM Row Boundary Extension registers
		each nybble is concatenated with the corresponding DRAM Row
		  Boundary register to form a 12-bit boundary value (of which
		  only the low 10 bits are actually used)
 6Ch	DWORD	reserved (hardwired to 00000000h)
 70h	BYTE	Error Command (see #01060)
 71h	BYTE	Error Status (see #01061)
 72h	BYTE	System Management RAM control (see also #01123)
		bits 7-6: reserved
		bit 5:	map SMM-mode memory (64K) into address space when bits
			2-0 = 010 (default 3000h:0000h; can be changed by
			first SMM event)
		bit 4: close SMRAM space (allows data accesses to be forwarded
			to PCI bus while execuding SMM code)
		bit 3: lock SMRAM space (can't be cleared by software)
		bits 2-0: SMRAM memory address (010 = Axxxxh, 011 = Bxxxxh)
 73h  5 BYTEs	reserved
 78h	WORD	Memory Space Gap
		bit 15: enable ISA hole
		bits 14-12: size of ISA hole in MB (less 1); must be power of 2
		bits 11-8: reserved
		bits 7-4: bottom of ISA memory hole in MB
			  (must be multiple of gap size)
		bits 3-0: reserved
 7Ah  2 BYTEs	reserved
 7Ch	DWORD	Frame Buffer Range (see #01062)
 80h 128 BYTEs	reserved
Note:	the 82434NX is part of the Intel Neptune chipset
SeeAlso: #01064,#01083