Bitfields for Intel 82443BX SDRAM Control Register:
Bit(s)	Description	)
 15-10	reserved (0)
 9-8	add one-clock delay to idle/pipeline DRAM leadoff when =01 (all other
	  values are illegal)
 7-5	SDRAM mode select
	000 normal operation
	001 issue NOP command on all CPU-to-SDRAM cycles
	010 issue All-Banks-Precharge command on all CPU-to-SDRAM cycles
	011 issue mode register set command on CPU-to-SDRAM cycles
		(command is driven on memory address lines, so the proper
		address must be calculated for each row of memory to drive
		the correct command; MAx[2:0] must be driven to 010 for
		burst-of-4 mode, MAx3 to 1 for interleave wrap type,
		MAx4 to the value of the CAS# latency bit, MAx[6:5] to 01,
		and MAx[12:7] to 0000000
	100 issue CBR cycles on all CPU-to-SDRAM cycles
	else reserved
 4	"SDRAMPWR" specifies how CKE signals are driven for various DRAM
	  configurations; refer to #01145 bit 5
 3	Leadoff Command Timing
	=0 four CS# clocks (100 MHz or 66 MHz desktop if MAA/MAB load > 9)
	=1 three CS# clocks (66 MHz mobile platforms, or desktop w/ load <= 9)
 2	CAS# latency
	=0 three DCLKs
	=1 two DCLKs
 1	SDRAM RAS# to CAS# delay
	=0 three clocks
	=1 two clocks
 0	SDRAM RAS# precharge
	=0 three clocks
	=1 two clocks
SeeAlso: #01142