Bitfields for Intel 82443BX (Device 0) NBX Configuration Register:
Bit(s)	Description	)
 31-24	SDRAM rows without ECC; each set bit indicates a row in the SDRAM array
	  with does NOT have error correction (bit 24 = row 0; note that double-
	  sided DIMMs use two rows, one for the front and one for the back)
 23-19	reserved
 18	DRAM data asserted on host bus on the same clock on which the snoop
	  result is sampled, instead of one clock later
 17	ECC signals are always driven for EDO memory
 16	IDSEL redirection
	=0 allocate IDSEL1/AD12 to bridge, never assert external AD12
	=1 allocate IDSEL7/AD18 to bridge, never assert external AD18; PCI
	  configuration cycles for Bus0/Device7 are redirected to Bus0/Device1
 15	disable WSC# handshake (uni-processor mode)
 14	Intel Reserved
 13:12	Host/DRAM frequency
	00  100 MHz
	01  reserved
	10  66 MHz
	11  reserved
 11	enable AGP-to-PCI access (note: AGP-to-PCI traffic is not allowed to
	  target ISA-bus devices)
 10	disable PCI agent access to graphis aperture (ignored if bit 9 clear)
 9	global enable graphics aperture access
 8:7	DRAM Data Integrity Mode
	00 non-ECC
	01 error checking only (e.g. parity)
	10 ECC mode
	11 ECC mdoe with hardware scrubbing
 6	enable ECC diagnostics mode (when set, ECC lines are forced to zero on
	  writes and compared to internally-generated ECC on reads)
 5	monochrome video adapter present on PCI/ISA bus (with primary adapter
	  on AGP bus)
	if register 3Eh bit 3 is clear, all VGA cycles are sent to PCI
	  regardless of this bit
	otherwise: if clear, all VGA cycles are sent to AGP; if set, all VGA
	  cycles except MDA ranges (memory B0000h-B7FFFh and ports 03B4h,03B5h,
	  03B8h,03B9h,03BAh,03BFh) are sent to AGP
 4	reserved
 3	enable posting of host USWC (U??? Speculative Write Combine) writes to
	  PCI memory
 2	In-Order Queue Depth
	=1 maximum (PPro supports up to 8, but 82443BX only supports depth 4)
	=0 depth forced to 1 (no pipelining on processor bus)
 1:0	reserved
SeeAlso: #01142