Bitfields for OPTi 82C750 Vendetta (device 1) cycle control:
Bit(s)	Description	)
 15	ISA bus ROM write enable
 14	hidden refresh enable
 13-12	ATCLK select
	00 = LCLK/4
	01 = LCLK/3
	10 = LCLK/2
	11 = LCLK
 11	CPU master to PCI slave write
	0 = 1 LCLK
	1 = 0 LCLK
 10-8	PCI master to PCI master preempt timer
	000 = no preempt
	001 = 260 LCLKs
	010 = 132 LCLKs
	011 = 68 LCLKs
	100 = 36 LCLKs
	101 = 20 LCLKs
	110 = 12 LCLKs
	111 = 5 LCLKs
 7	reserved
 6	XDIR achieve
	0 = accessing ROM, keyboard controller, RTC
	1 = accessing ROM, NVRAM
 5	PERR# to SERR# conversion enable
 4	address parity checking enable
 3	target abort SERR# generation enable
 2	fast back-to-back enable
 1	sample point decoding
	0 = slow
	1 = subtractive
 0	reserved
SeeAlso: #00939