Format of PCI Configuration Data for Intel 82441FX:
Offset	Size	Description	)
 00h 64 BYTEs	header (see #00878)
		(vendor ID 8086h, device ID 1237h) (see #00873)
 40h 16 BYTEs	reserved
 50h	WORD	PMC Configuration (see #01230)
 52h	BYTE	deturbo counter control
		when deturbo mode is selected (see PORT 0CF9h), the chipset
		  places a hold on the memory bus for a fraction of the
		  time inversely proportional to the value in this register
		  (i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.)
 53h	BYTE	DBX buffer control (see #01231)
 54h	BYTE	auxiliary control (see #01232)
 55h	WORD	DRAM Row Type (see #01233)
 57h	BYTE	DRAM Control (see #01234)
 58h	BYTE	DRAM Timing (see #01235)
 59h  7 BYTEs	Programmable Attribute Map registers 0-6 (see #01118)
 60h  8 BYTEs	DRAM Row Buondary registers 0-7
		each register N indicates cumulative amount of memory in rows
		  0-N (each 64 bits wide), in 8M units
 68h	BYTE	Fixed DRAM Hole Control
 69h  7 BYTEs	reserved
 70h	BYTE	Multi-Transaction Timer
		number of PCLKs guaranteed to the current agent before the
		  82441 will grant the bus to another PCI agent on request
 71h	BYTE	CPU Latency Timer (see #01236)
 72h	BYTE	System Management RAM control (see #01123)
 73h 29 BYTEs	reserved
 90h	BYTE	Error Command (see #01237)
 91h	BYTE	Error Status (see #01238)
 92h	BYTE	reserved
 93h	BYTE	Turbo Reset Control (see #01239)
 94h 108 BYTEs	reserved
SeeAlso: #01098,#01108