Bitfields for AMD-645 Miscellaneous Control 1 register:
Bit(s)	Description	)
 7-5	reserved (0)
 4	enable command register test mode
	(when set, PCI offset 04h bits 0-1 become writable and bit 3 read-only)
 3-2	reserved (0)
 1	disallow interruptions of PCI burst reads
 0	enable posted memory writes
SeeAlso: #01011,#01019,#01020