)
Values for Intel 82371MX Shadow Register
Value	AT Port	Description
 00h	00h	Channel 0 Base Address Register (low byte)
 01h	00h	Channel 0 Base Address Register (high byte)
 02h	01h	Channel 0 Base Word Count Register (low byte)
 03h	01h	Channel 0 Base Word Count Register (high byte)
 04h	02h	Channel 1 Base Address Register (low byte)
 05h	02h	Channel 1 Base Address Register (high byte)
 06h	03h	Channel 1 Base Word Count Register (low byte)
 07h	03h	Channel 1 Base Word Count Register (high byte)
 08h	04h	Channel 2 Base Address Register (low byte)
 09h	04h	Channel 2 Base Address Register (high byte)
 0Ah	05h	Channel 2 Base Word Count Register (low byte)
 0Bh	05h	Channel 2 Base Word Count Register (high byte)
 0Ch	06h	Channel 3 Base Address Register (low byte)
 0Dh	06h	Channel 3 Base Address Register (high byte)
 0Eh	07h	Channel 3 Base Word Count Register (low byte)
 0Fh	07h	Channel 3 Base Word Count Register (high byte)
 10h	08h	DMA1 Command Register
 11h	0Bh	Channel 0 Mode Register
 12h	0Bh	Channel 1 Mode Register
 13h	0Bh	Channel 2 Mode Register
 14h	0Bh	Channel 3 Mode Register
 15h	0Fh	DMA1 Mask Register
 16h	C4h	Channel 5 Base Address Register (low byte)
 17h	C4h	Channel 5 Base Address Register (high byte)
 18h	C6h	Channel 5 Base Word Count Register (low byte)
 19h	C6h	Channel 5 Base Word Count Register (high byte)
 1Ah	C8h	Channel 6 Base Address Register (low byte)
 1Bh	C8h	Channel 6 Base Address Register (high byte)
 1Ch	CAh	Channel 6 Base Word Count Register (low byte)
 1Dh	CAh	Channel 6 Base Word Count Register (high byte)
 1Eh	CCh	Channel 7 Base Address Register (low byte)
 1Fh	CCh	Channel 7 Base Address Register (high byte)
 20h	CDh	Channel 7 Base Word Count Register (low byte)
 21h	CDh	Channel 7 Base Word Count Register (high byte)
 22h	D0h	DMA2 Command Register
 23h	D6h	Channel 5 Mode Register
 24h	D6h	Channel 6 Mode Register
 25h	D6h	Channel 7 Mode Register
 26h	DEh	DMA2 Mask Register
 27h	20h	PIC1 ICW1
 28h	21h	PIC1 ICW2
 29h	21h	PIC1 ICW3
 2Ah	21h	PIC1 ICW4
 2Bh	20h	PIC1 OCW2
 2Ch	A0h	PIC2 ICW1
 2Dh	A1h	PIC2 ICW2
 2Eh	A1h	PIC2 ICW3
 2Fh	A1h	PIC2 ICW4
 30h	A0h	PIC2 OCW2
 31h	70h	NMI mask / RTC address
 32h	03FAh	COM1 FIFO Enable Register (only bits 0,3,6 & 7 valid)
 33h	02FAh	COM2 FIFO Enable Register (only bits 0,3,6 & 7 valid)
 34h	03EAh	COM3 FIFO Enable Register (only bits 0,3,6 & 7 valid)
 35h	02EAh	COM4 FIFO Enable Register (only bits 0,3,6 & 7 valid)
 36h	40h	TIMER 0 Count Register (low byte)
 37h	40h	TIMER 0 Count Register (high byte)
 38h	20h	Master PIC OCW3 Register (bits 0,2 & 5 only valid)
 39h	A0h	Slave PIC OCW3 Register (bits 0,2 & 5 only valid)
Desc:	This register is used to read the current programmed value of certain
	  AT compatable I/O ports which are traditionally write-only.
Note:	To read a given register, write the value from the table to the shadow
	  register, then immediately re-read the shadow register. The returned
	  value is the current value of the I/O port.
SeeAlso: #01168,PORT xxxxh"Intel 82371"