X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to; bh=iIjtryzPV4wkIIv9ALpS2UQ3+SqWD61kA+1LxnguzQQ=; b=dt8Yp2Btz+a2apduokEMFfzC4T0X/GvMDOCprAwJtrwdM9uOTidaWHDA1L07bL/ADE elXf+5b++UnyibYsgM+F7LOFDdFD61ZISvBYuhHhlsWOke/BPUydmTyJONAJU3sAutID fhFuRSn5UDcBCRcFkuOotGlvFjK4o+9bz1yC3OpQDDZ8sdfAAndzNyeIawqLWC2VbMBP QmNNgTEIz3DLd+V3C48adEsLIbEzC+OPebjP8phTXR2YQvil6OQTw1heENuAd/CR5HRL u0N9Y7TnwVroxfCHcTCEi8fDuRPsDc8lB7IwnJRF55XdqamI4BZNGnLV8xi0vWrht/nI 6VrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=iIjtryzPV4wkIIv9ALpS2UQ3+SqWD61kA+1LxnguzQQ=; b=PABMAsyTwPz4rs53lSMlXvhymL64ZgkKQBitG+hPQ/hXvIyhEnu2thhzr1HbQ+xGRK dscl3/Jy6LKF/nQL0q9u+KCJcnjst/37bzfzIyhPrVV89xsbeuJxyXFnj/NWo63FP7cM LGV/Gf6qYVpLBF7wD/soglMoP9QnuMUu0fROLcG6PpH7PDQPoixCSgoQ5z4j7V1Llaqp C1ZgRwD9X5ExHBsesW8i/b1DDk4jkJabqVnWSSIAjqBePeegN1QED3LOXydGXSbiap1S HuRHHV7huRJmVdqAtMCtjCrbKnXaZ+gettlvEF26rv5B2bV0HtsYAkcag6v+4lSHf1+H dU5A== X-Gm-Message-State: AN3rC/6kv6nuStzovLHk+ZSVWjT/frXK8vy7YjqPg2AdelXOUxXEYknK Zty0VGM8LciQJWi8PkM1zFdZOWeYbQ== X-Received: by 10.157.18.168 with SMTP id g37mr7641917otg.261.1493188927640; Tue, 25 Apr 2017 23:42:07 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: "Erich Heinzle (a1039181 AT gmail DOT com) [via geda-user AT delorie DOT com]" Date: Wed, 26 Apr 2017 16:12:07 +0930 Message-ID: Subject: Re: [geda-user] Slots in plane To: geda-user Content-Type: multipart/alternative; boundary=94eb2c03bfd69d5995054e0c237b Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk --94eb2c03bfd69d5995054e0c237b Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Quoting myself from the last time it came up, slots can be achieved via post processing of excellon drill files during/following gerber export It can be done with:https://github.com/hackvana/eagle-plated-slots/blob/mas= ter/eagle-slots.py which looks for a magic, pre-defined drill size as a trigger to create a slot joining a pair of consecutive holes of that size where before there were just two holes in the drill file. The above script was written by my usual pcb supplier, hackvana, who hangs out in #hackvana on freenode, i.e. this is a technique supported by an actual pcb supplier See also: http://www.delorie.com/archives/browse.cgi?p=3Dgeda-user/2015/03/03 Cheers, Erich. On 25 Apr 2017 1:52 am, "McKay, Roy L [PHYSA] (mckay AT iastate DOT edu) [via geda-user AT delorie DOT com]" wrote: Thanks for the suggestions. None of them work as I had done in the past. Looking at the board I pulled this stunt, I had 5 layers with no copper under the traces in one signal plane. The pcb files show holes for the =E2=80=9Canti=E2=80=9D traces. (The detail of the holes is large enough I = know I did not use the hole function.) I recall placing the traces in each layer, perform some magic (like MorphPolygon) and done. No editing gerbers. No zero width traces. Once again, should have noted what I did. Any other ideas from people? Thanks, RM --94eb2c03bfd69d5995054e0c237b Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Quoting myself from the last time it came up, slots can be achieved via =
post processing of excellon drill files during/following gerber export

It can be done with:
https://github.com/hackvana/eagle-plated-slots/blob/master/eagle=
-slots.py

which looks for a magic, pre-defined drill size as a trigger to create a sl=
ot joining a pair of consecutive holes of that size where before there were=
 just two holes in the drill file.
The above script was written by my usual pcb supplier, =
hackvana, who hangs out in #hackvana on freenode, i.e. this is a technique =
supported by an actual pcb supplier

See also:
http://www.delorie.com/archives/browse.cgi?p=3Dg=
eda-user/2015/03/03
Cheers,

Erich.


O= n 25 Apr 2017 1:52 am, "McKay, Roy L [PHYSA] (mckay AT iastate DOT edu) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> wrote:

Thanks for the suggestions.=C2=A0 None of them work = as I had done in the past.=C2=A0 Looking at the board I pulled this stunt, = I had 5 layers with no copper under the traces in one signal plane.=C2=A0 T= he pcb files show holes for the =E2=80=9Canti=E2=80=9D traces. =C2=A0(The detail of the holes is large enough I know I did not use the hole function= .) =C2=A0I recall placing the traces in each layer, perform some magic (lik= e MorphPolygon) and done.=C2=A0 No editing gerbers.=C2=A0 No zero width tra= ces.

=C2=A0

Once again, should have noted what I did.<= /u>

=C2=A0

Any other ideas from people?

=C2=A0

=C2=A0=C2=A0 Thanks,

=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 RM


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