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Date: Wed, 18 Jan 2017 08:17:30 +0100 (CET)
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From: gedau AT igor2 DOT repo DOT hu
Subject: Re: [geda-user] [pcb] why no clearpoly on silk
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Hi all,

sligtly related to the disappearing silk poly: we do not let polygon 
clearance happen on silk. It's disabled even if both clearline and 
clearpoly are set. Does anyone remember what was the reason for 
this? Is it only that it "doesn't seem practical"? If so, why don't we 
just let the user control this with those flags we already have?

(The relation is that the bug can not be reproduced if the clearpoly flag 
is not set on the silk poly.)

I'm asking this because I am planning to remove this limitation in 
pcb-rnd and let users do clearpoly in whatever layer they want to.

Regards,

Igor2