X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to; bh=70g6JXK0Ii79x5uEI7WSnrO/4asaODcOBqzzNEmAqcE=; b=tKAigu9TwlI3kcwTmCaCF1TjdzyKxJCUS3SVLkzjpk+SwbRO6Dn32NHUtjI1fGHYmE MpORIn9kYvurpDPEBSufVwVur8S0/51MQv3mf0zz8TxQUAKWFnGPaK5jcMMyoFC9Suvj OXqiCyIWFNrQdR3QgF3GxBFt0xgiDPqtHssmAoKEV89bZkJQpojYxQnz71Y7gJJ6ju5G 9pEeMPn6J09UR17oNOeqqr77fInRA7AHy6Eb8Rgw9sQiRZ318rIggriH/+Owr+PTnsp3 NPAZhXLr29S0QHOX5ttZ7XD6/D1+2MhewlaC4auiRQV3H+oRSVuLIgDe/9G4clf0fpVI 9ceg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=70g6JXK0Ii79x5uEI7WSnrO/4asaODcOBqzzNEmAqcE=; b=fAY5FdK0u8LScfQ1qYd/UKBoCRyQ6Micg8oNrRMXVL9Hlj6yrQOrV2+oJyssmY22iz sUo/y4YgtwtZrGHrRYpWPOD60DRAuZ21xtmA430p54f4Tv4dFqIsGpqp029ekebzL//N px3TqWrbMQEDmdO6WDK8MwMscxyeM+JWpki9VeQd34s6aMRQWct4Jq1DVAYqVKZ9RAYh ysbrSgjafnHS5eYKsluGdOgbKQkkYRx7BO/Ud8XC5lACKia02j9xhOsRSvNSZTRWZoef yIqRuHExyl1frqD0IbE0LBsUWv28FirHv+E6qQQHp3YcWjynCssFhwbDWw4RPjODJXGr I+7g== X-Gm-Message-State: AE9vXwPCjeTtcZTyhrJJ/1UYveT/hjxSWC+OH3xx98pMRlK8qcRTh2wp7G18QTJTMqKP3sv/q5d1CxrCpD4iOA== X-Received: by 10.25.16.92 with SMTP id f89mr2114874lfi.143.1472263498269; Fri, 26 Aug 2016 19:04:58 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <57C09C3C DOT 7020708 AT xs4all DOT nl> <20160826171545 DOT 2bc54995 AT floyd DOT freeelectron DOT net> From: "Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" Date: Sat, 27 Aug 2016 02:04:57 +0000 Message-ID: Subject: Re: [geda-user] Microwave PCB layout simulation or How to eat all your processing power in 3 easy steps To: gEDA users mailing list Content-Type: text/plain; charset=UTF-8 Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Fri, Aug 26, 2016 at 10:48 PM, Chad Parker (parker DOT charles AT gmail DOT com) [via geda-user AT delorie DOT com] wrote: > FWIW, this is something I've thought a lot about also. It would be very > cool, but as with all simulation, to do it and get an answer out that > actually resembles the real world is really hard. There are a lot of details > that have to be taken into account, and then you have to make sure that your > fab gets them all right too when you build the board. You can get maybe 10% > variation in the dielectric constant of FR4, for example. PCB is not > currently aware of many of those details, like board material, layer > thickness, the amount of prepreg between the layers, etc. so you'd still > have to add all that information in somewhere. To do this we would have to write a geometry export engine from pcb-* to what ever format the meshing tool used with the FEM tool uses. (in the case of openems it is built in) FEM is all about meshing. The geometry is meshed and then like in spice a FEM solvers build a jacobian is and nodes in it processed. Just like in spice there are time step errors but also, mesh type, mesh density, and boundary conditions all of which you can get wrong and still have a valid looking result. What I am getting at is that like spice (only more so) it is very easy to have the program run and produce convincing but bogus results. These draw backs are not unique to openems they are a universal to the FEM experience. Every FEM comes with caveats about how it's use case and people violate them all the time with out knowing. Once worse they get blinded by how pretty the graphs are and they believe them because of how magical it all looks. I am in favor of this as a long term goal. I am just saying yes you are right but the real problems with FEM are deeper than 10% variations in FR4's dialectric from the specs nominal. Anyone doing microwave layout would have to deal with that variation or use a Rodgers composite (ceramic). Board material, layer thickness and etc. are all things that we can have people define and then include in the export. Yes they will vary in the real world but it's like anything else the users need to account for that. > I have a situation right now where I'm putting a couple of vias in close > proximity to each other and counting on the parasitic capacitance to couple > in a test signal. I'd love to be able to simulate and get an idea of what > the capacitance actually is. I'll have to build and test it to really figure > it out. That is what I really care about but the parasitics are different at different frequencies. There used to be a FDTD solver called LC issued by Cray. Sadly Cray killed it off but I can give you the email address of the guy who wrote it and if you ask politely he might send you a copy. It took in gerber format and returned augmented spice netlists with the parasitics added. > BTW, you need more than just Hyperlynx to do this. You need the specific > Hyperlynx 3D field solver module. My employer has licenses for MG, including > Hyperlynx, but that module is licensed separately (I was just looking into > this last week). I was not saying we should add hyperlynx. Please read my other email in this thread replying to Bert on that. The only reason hyperlynx has come up is that one example I linked to used it with an open source hyperlynx to openems conversion tool. > I don't know much about gnucap, but it seems like in order to use it to > simulate a PCB like this, you still need to be able to abstract a circuit > model from the layout, and that's what the fancy, expensive programs do. You are imaging something larger than I was proposing. I would like to do what you are talking about but for a lot of people would be happy to test if the distributed element filter they have drafted works. > --Chad > > On Fri, Aug 26, 2016 at 5:15 PM, al davis wrote: >> >> On Fri, 26 Aug 2016 21:45:00 +0200 >> "Bert Timmerman (bert DOT timmerman AT xs4all DOT nl) [via geda-user AT delorie DOT com]" >> wrote: >> > So basically you wish for a Hyperlynx exporter for pcb ;-) >> >> Good luck getting Mentor (owner of Hyperlynx) to do that. >> >> What you really need is an exporter to gnucap-Verilog, or a plugin for >> gnucap to read (and write) the pcb format. >> >> If somebody wants to write that gnucap plugin, I will help you do it. >> > -- Home http://evanfoss.googlepages.com/ Work http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/ -----BEGIN PGP PUBLIC KEY BLOCK----- Version: GnuPG v2 mQENBFYy4RYBCAC183JomLtbdAlcKiaPDoVHq52LDmVmH75aiEc69m7YxDt54/ai VtYCAobbGVIyn3Hlz3uhF6LnPl/6Lm1VdnCfpwu3KQhCO6ds10ow2C30X4ohCqOd hCVg5C+ILmQkEffFrFODy3ji+PYTF4pADvHCWsTMv0hf0llwFOJsBCK6cl02IffE JPqy4PjM1nZ9HpzT84JBaG/4OGvTZ8SQ2yFUl265jagvygPTf88H1xpZHH1r8dB1 stjUHLmPH8AOyDgKxFchgGeDc3p/vJtgDDIXAFfDXG0NSRovLmtaQdGxe47Zf/go bXiEM7YL2WqQe5zfEA919JxkEwlDKYniOSVzABEBAAG0N0V2YW4gRm9zcyAoVGhp cyBpcyBteSBwdWJsaWMga2V5LikgPGV2YW5mb3NzQGdtYWlsLmNvbT6JATkEEwEC ACMFAlYy4RYCGwMHCwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCIpQTcE8nN bbBaCACAm8pU5lG1ev2Fsw68Axtcl57SJrYieqX96c3YuYH9JpqMqJRnd9nDKw9X tQuvuH7tUk0VbOaDqReOYJVI/4c5wb9AaOFp6K2DUcupq6XhgXpvz3HzoPwjAdIj XuQzdRUx5+innTJrSkGuBYW/CZ2zqEx4xfLlq4rO0hoTUMR8QVp2cCrkw6BT0m86 APIw/ZnjoxM8IEzr7MxfRIg3qpzrZk28rmhx+k78Jyk61UhwcCPGIm/pjUopTwYJ 3YBdRB2cYD2aN7A1JVf5cRmSQYooHBGpH0kYvomGk97PKqypVuJ7OpG9xM58wUcC qUVt9hKlePLzP8csYjt8onqI7qIIuQENBFYy4RYBCADlH8spG3WkCx62vB5mr5Z0 SCDd/RcyA4A5y5EOj5KurQkrSWpgi9Ho1yKruMJ6blQR2qkc66KqH9pnXDm/ZI1M K/wdW3ngETxBmXoozzFMT89aEWIVR5/PFodWK1elekE9iJxACuR98Zg2QttTD3x8 A9w8VEyMLOXcDTrPFpHegMKswFBg5iuMulAdXAoGejWTI3n+qKFpabHm2Lfs6wjk 5rjucpTdeFK6UeWF1xAvNxXibuu5BlGwv53930qIXRwO/Gn2Rh5DXWxKU2fEIme/ xgQQmIsDeUoWbfybdjw/x7Q0LW4mINiLDQcGHHRQKFIxbAJCT3USPLGh5xwE9/Er ABEBAAGJAR8EGAECAAkFAlYy4RYCGwwACgkQiKUE3BPJzW0uYAf9Hf30n8tM3mR2 Zo6ESE0ivgdgjaJtAWrBUx7JzAzPjBnBOlNnu5Y9lVEqetvUPH6e3PvaHYUuaUU8 0HwxuKBW9nUprgV6uIu1DZmlcp+SxpbuCy7RDpNocRLNWWFMaYYzznmTgfnTgD4D gCq8Mf1mcfrluTkOAo+QNqbMfl1GISClopRqxVuAo59ewgMnFujwgd8w12BwWl24 CzqOs5HqcUslePj+LzcjSNgVCklYwKl+0dsb/fctMOCtHodwqm2CBJ+zydvNmYkD fxda/J91Z1xrah5ec++FL0L4vs+jCiIWJeupJFKlr1hCMZiiGH7W554loK5l4jv3 EY347EidAw== =Ta4p -----END PGP PUBLIC KEY BLOCK-----