On Aug 2, 2016, at 4:01 PM, Ouabache = Designworks (z3qmtr45 AT gmail DOT com)= [via geda-user AT delorie DOT com] = <geda-user AT delorie DOT com>= wrote:

On Tue, Aug 2, 2016 at 11:56 AM, John Doty <jpd AT noqsi DOT com> wrote:

On Aug 2, 2016, at 2:18 PM, Ouabache Designworks (z3qmtr45 AT gmail DOT com) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> = wrote:

On Tue, Aug 2, 2016 = at 10:27 AM, John Doty <jpd AT noqsi DOT com> wrote:

On Aug 2, 2016, at = 11:55 AM, Ouabache Designworks (z3qmtr45 AT gmail DOT com) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> = wrote:

This group has shown = almost no interest in features that are needed by IC designers if they = are not also needed by PCB designers.

What do you imagine IC = designers need? I design mixed-signal ASICs in gschem, and do not = perceive any limits. Just another application for a complete, general = purpose network topology editor.

John = Doty = = Noqsi Aerospace, = Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com

How about libraries that you can download = that don't have naming collisions with other = libraries?

Since you = have complete control of your library path, why is this a problem? Just = put together the library *your* project needs. No big deal. Certainly = not something that requires a new *feature*.

So I = need part A from Library foo and part B from library bar when both libs = have both parts. How do I set up the search = path?

The way I = do it is to have a project symbol directory. I copy the necessary = symbols from libraries into there. It=92s safer to keep specialized = symbols bundled with the project anyway. Libraries get = revised.

How about = Busses? IC's need support for wires,vectors and busses. Gschem does = wires with some graphic support for vectors but nothing for = busses.

Need? Maybe = they would be nice, but I haven=92t really missed them. Mostly you want = them in complex digital parts, I think. If that was the kind of chip I = was doing, I=92d do those straight in HDL, not draw them in gschem. In = any case, there=92s nothing preventing you giving a net a name that = describes a bus, and dealing with that downstream.

Wir= es and vectors have inputs and outputs. Busses have masters and = slaves. You need to support bundling wires,vectors and busses into = bigger busses, passing it up and down hierarchies and then splitting = everything back apart at the = end.

Analogues of = some of that are in my experimental gnetlist back end for drawing = Makefiles. It=92s just a matter of a little Guile scripting, = really. http://www.delorie.com/archives/browse.cgi?p=3Dgeda-user/2015/= 10/12/13:53:03. =93Net=94 lines don=92t need to know much about what = they represent when they can learn from the pins connected to = them.