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From: geda AT psjt DOT org (Stephan =?utf-8?Q?B=C3=B6ttcher?=)
To: "michalwd1979 \(michalwd1979\@o2.pl\) \[via geda-user\@delorie.com\]" <geda-user AT delorie DOT com>
Subject: Re: [geda-user] Wilkinson splitter - how to implement and use?
References: <23abdc31 DOT 72365e7a DOT 572529a9 DOT 212e2 AT o2 DOT pl>
	<a5562efe70ac4b83b066facd19a46167 AT gwp>
Date: Mon, 01 Aug 2016 21:28:57 +0200
In-Reply-To: <a5562efe70ac4b83b066facd19a46167@gwp> (michalwd's message of
	"Mon, 1 Aug 2016 15:53:23")
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"michalwd1979 (michalwd1979 AT o2 DOT pl) [via geda-user AT delorie DOT com]"
<geda-user AT delorie DOT com> writes:

> Dear Members,
>
> I need to design a RF board with some Wilkinson splitters on it. While
> the symbol of splitter is ready (rf/splitter-1.sym) and for pcb we
> have even a java generator
> (https://github.com/erichVK5/WilkinsonPowerDividerFootprintGenerator),
> I'm not sure how to use it. The splitter is just a few fancy tracks on
> pcb (plus a resistor) that in fact are all connected. In schematics
> however this is an element with 3 pins. In pcb I can not name the
> splitter pins "1", "2", "3", because this will give warnings about
> shorted nets. If I change schematics symbol (short its pins) there
> will be no warnings but all RF nets are reduced to one - that is not
> the case (all splitter input/output connections are lost).
>
> Is there a better/preferred way to deal with such RF components in
> gEDA?

you could put the RF component traces on an extra layer.  During design,
that layer would be kept separate.  For checkout the layer must be put
into the group of the copper layer.

Not perfect, but can work as is.  The RF component traces cannot be part
of a footprint, though.

> Thanks in advance,
> Michael Widlok

Gruß,
-- 
Stephan