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Date: Mon, 07 Mar 2016 12:14:22 +0100
Message-ID: <20160307121422.Horde.pcjHU6fmK16LcDwrtNXFAbn@webmail.in-berlin.de>
From: Hagen SANKOWSKI <hsank AT nospam DOT chipforge DOT org>
To: "Peter Clifton (petercjclifton AT googlemail DOT com) [via
 geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Subject: Re: [geda-user] hierarchical design - two symbols pointing to one
 schematic
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Reply-To: geda-user AT delorie DOT com

Hello Peter.

I did some stuff with the (unvisible) nets like VDD and GND for my  
symbols and got
out of this error.
And yes, there is no recursivity inside.
The tool just ate all the memory while renaming ports and nets which  
are instantiated many times.. IMHO

Currently I try to layout my board and have seen some strange  
shortages between nets
I did not understand jet.

So maybe I came up with similar problems today evening while  
investigate the netlist stuff again.

Thanks for your help so far!

Regards,
Hagen.

Zitat von "Peter Clifton (petercjclifton AT googlemail DOT com) [via  
geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>:

> Regarding the OOM killing...
>
> I'm not certain that gnetlist checks for loops in your heiearchy of
> schematics.
>
> If you have inadvertently created a heirarchy which includes some parent
> schematic as a descendent of itself, I believe you can get gnetlist to spin
> on a loop eating memory.
>
> Peter



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"They who can give up essential liberty to obtain a little temporary
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