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Date: Sun, 13 Sep 2015 19:07:38 -0400
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From: DJ Delorie <dj AT delorie DOT com>
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In-reply-to: <91B6F5DA-94D6-4391-888A-7B057C76985E@noqsi.com> (message from
	John Doty on Sun, 13 Sep 2015 16:57:14 -0600)
Subject: Re: [geda-user] RFC: pin attribute remapping
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> But the combination of refdes and slot does. That's the reason for
> the slightly messy complication of using the pin number *after* slot
> expansion. Remember that this proposal is not recursive: it
> preserves the original refdes and slot as defaults a GUID.

> >  Saying "the U4 that had pin 2" might work,
> > unless we do away with numberic pins in favor of symbolic ones, then
> > all four gates have pins A,B,Y - not unique either.  With a symbolic
> > light symbol like that, pin and gate assignment might happen much
> > later, so device "U4" on the layout might include gates from U3, U7,
> > U5, and U14.
> 
> Yes.

Except in this case, we don't have any slot information in the
original schematic as a basis for annotating :-P

Consider a schematic with two gates, each U4 with pins A,B,Y.  I've
assigned one of them to pins 1,2,3 in gnetlist/PCB.  Tell me which one ;-)

> > However, I'm guessing heirarchical layout could be arbitrarily complex
> > in itself.  It would be nice to only have to layout each subsection
> > once and have that repeat, but that assumes each section can be laid
> > out exactly the same.  The ASIC folks seem to have this down pat but
> > their tools are already more complex than ours.
> 
> The thing that makes it easier in ASIC is that there aren't
> slots. If I want three NAND gates in a module, I draw three NAND
> gates. I don't have to worry about allocating gates between quads.

True.  Likewise for simulations.  But I was referring to the layout
process, where blocks of functionality are laid out as blocks,
replicated all over, and connected up as a separate step.  It would be
cool to be able to do that in a board layout package as well.