X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-TCPREMOTEIP: 207.224.51.38 X-Authenticated-UID: jpd AT noqsi DOT com Content-Type: text/plain; charset=windows-1252 Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.6\)) Subject: Re: [geda-user] RFC: pin attribute remapping From: John Doty In-Reply-To: <201509132209.t8DM95OE004193@envy.delorie.com> Date: Sun, 13 Sep 2015 16:57:14 -0600 Message-Id: <91B6F5DA-94D6-4391-888A-7B057C76985E@noqsi.com> References: <5D1C97FB-F049-4ABB-90E4-F2108647A111 AT noqsi DOT com> <201509131840 DOT t8DIecSf029011 AT envy DOT delorie DOT com> <201509132209 DOT t8DM95OE004193 AT envy DOT delorie DOT com> To: geda-user AT delorie DOT com X-Mailer: Apple Mail (2.1878.6) Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by delorie.com id t8DMvOMf013315 Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Sep 13, 2015, at 4:09 PM, DJ Delorie wrote: > >>> Aside from assigning GUIDs to each symbol as they're instantiated, I >>> don't have a good solution to this. >> >> The refdes assigned in the schematic is the GUID, just as >> always. Similarly, the pin number assigned in the symbol, after >> translation via the slot number assigned in the schematic, is the >> pin's GUID. Those don't change, but what the user sees in the >> graphics might. > > If you have a 7400, you already have four gates (and thus four > symbols) with the same refdes. It's already not a GUID (globally > unique identifer) because it's not even unique within the page, > because saying "U4" doesn't tell you which of those four symbols > you're referring to. But the combination of refdes and slot does. That’s the reason for the slightly messy complication of using the pin number *after* slot expansion. Remember that this proposal is not recursive: it preserves the original refdes and slot as defaults a GUID. > Saying "the U4 that had pin 2" might work, > unless we do away with numberic pins in favor of symbolic ones, then > all four gates have pins A,B,Y - not unique either. With a symbolic > light symbol like that, pin and gate assignment might happen much > later, so device "U4" on the layout might include gates from U3, U7, > U5, and U14. Yes. > If you want to do an as-built of that, you need to know > *which* U3 symbol, *which* U7 symbol, etc. Yes. The as-built tool would have to know to display a different refdes on reassigned instance. And throw an error if things aren’t consistent. > > The only way to let the refdes be a UID (much less a GUID) is to > enforce it in gschem and gnetlist - a hard error if you reuse one - > and assume that slotting is going to make a new, probably messy, > refdes in the layout. And that just makes the power pin problem > worse, plus stops people from splitting a large chip into mutltiple > symbols. > > In my sch2csv script, I use the X,Y coordinate of the symbol on the > page and the file it came from as it's GUID, assuming that two symbols > won't be in the same place on the same page, but even that's not > guaranteed to be unique. But at least "the U4 that's at 325,400" has > a better chance of picking exactly one symbol :-) > >> Good point. I think the solution is to allow the refdes to be a >> pathname. This already works downward, but, > > Yea, I figured no matter how messy identifiers turned out, identifiers > in a flattened heirarchy were going to be messier. You end up with at > best a refdes like CP7.A4.U3 for gate U3 in amplifier instance 4 of > control processor instance 7. > > The messiness could be partly controlled if the layout could designate > a region of the board as being a location in the heirarchy, so > shortcut refdes's could be used on the silkscreen. I.e. a region > would be outlined and the outline named "CP7.A4" and within that > outline, the text ".U4" would imply "CP7.A4.U4". > > However, I'm guessing heirarchical layout could be arbitrarily complex > in itself. It would be nice to only have to layout each subsection > once and have that repeat, but that assumes each section can be laid > out exactly the same. The ASIC folks seem to have this down pat but > their tools are already more complex than ours. The thing that makes it easier in ASIC is that there aren’t slots. If I want three NAND gates in a module, I draw three NAND gates. I don’t have to worry about allocating gates between quads. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ jpd AT noqsi DOT com