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Subject: Re: [geda-user] netlisting libraries (was:  memory planning and pcb file format)
From: John Doty <jpd AT noqsi DOT com>
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Date: Wed, 26 Aug 2015 12:21:43 -0400
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On Aug 26, 2015, at 10:37 AM, John Griessen <john AT ecosensory DOT com> wrote:

> Think of the non-standard use case of creating a FPGA schematic that replaces a discrete logic chunk
> with a module that is only in verilog:
> Save the discrete logic to a new sch file, create a symbol for the verilog chunk,

For SPICE, using gnet-spice-noqsi, it would be the same symbol for the model and the schematic. The choice would be which subcircuit file you include in the simulation.

> connect up after deleting the discrete logic, generate a new netlist. Generate a new netlist for the
> discrete part.
> 
> Now you want to check things.  This is all new code for future.
> 1. generate a simulatable verilog-ams netlist from the verilog chunk.
> 2. create a simulation version schematic and generate simulatable verilog-ams netlist from the top interconnect.

Why a simulation version of the schematic? You may need a separate schematic as a simulation “test fixture”, but your simulation netlister should be able to handle an ordinary schematic, with appropriate simulation attributes, as input. Since gnetlist back ends generally ignore attributes they don’t recognize, that isn’t much of a problem. The overloading of pinseq is really the only one I’ve found troublesome, so gnet-spice-noqsi gives you other ways to handle slotted devices.

> 3. concatenate and simulate together
> 4. create a simulation version schematic and generate simulatable verilog-ams netlist from the discrete logic.
> concatenate discrete logic verilog-ams netlist and verilog-ams netlist from the top interconnect.
> 5. They should be equal.

I’ve done similar things comparing SPICE subcircuits extracted from IC layout to SPICE subcircuits generated from schematics. There’s no barrier to doing this.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com