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Date: Tue, 29 Nov 2011 00:39:37 -0500
From: Vanessa Ezekowitz <vanessaezekowitz AT gmail DOT com>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] Modern GAL/PAL design with gEDA?
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On Mon, 28 Nov 2011 19:18:08 -0600
John Griessen <john AT ecosensory DOT com> wrote:

> On 11/28/2011 02:07 PM, Vanessa Ezekowitz wrote:
> > after a week of wrangling with this, I finally turned out a working
> > design - or at least, it simulates (iverilog + gtkwave)*and*  synthesizes
> > properly
> 
> Hey, you did it!
> Looks like dotclock is a sequence you create after being triggered so as to
> put out some stored values, right? and that sequence is done with #delay
> statements. (it's been 20 years since I was doing this daily to make iic
> ports, serial ports, etc...)
> 
> John

Actually, you're pretty close to what I was originally trying to do.  The RAM controller chip used in C64 (of course) RAM Expansion Modules only produces enough signals during refresh to handle the 256k x 1 RAMs the use, and in RAS-Only refresh mode at that.

So I had to detect those RAS-Only refresh signals and replace them with CAS-before-RAS pulses.  I originally tried to use a state machine driven by the dot clock, until I realized the 22v10's flip-flops are all clocked by the same line...  so a state machine was out.

I worked out that, assuming my testbench model is accurate, I could use the dot clock to directly drive the RAS output line as long as I pulled all of the CAS lines low first, and as long as I provided it in inverted form.  Since the 22v10 can't invert the clock line, I had to loop it through the chip and invert it that way.

The truly sad thing is the test bench is more complicated than the code it drives. :-)

-- 
"There are some things in life worth obsessing over.  Most
things aren't, and when you learn that, life improves."
http://digitalaudioconcepts.com
Vanessa Ezekowitz <vanessaezekowitz AT gmail DOT com>