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Date: Mon, 28 Nov 2011 23:01:09 -0500
From: gene glick <geneglick AT optonline DOT net>
Subject: Re: [geda-user] Modern GAL/PAL design with gEDA?
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Cc: Vanessa Ezekowitz <vanessaezekowitz AT gmail DOT com>
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On 11/28/2011 03:07 PM, Vanessa Ezekowitz wrote:
>
> Well after a week of wrangling with this, I finally turned out a working design - or at least, it simulates (iverilog + gtkwave) *and* synthesizes properly (ispLEVER under a virtual machine).  The funny part is, the final result (barring any last-minute bugs) is far smaller than what I first came up with.
>
> As an aside:  whoever wrote ispLEVER's error messages needed a lesson in user friendliness. :-)
>
> For those interested, the Verilog code is attached.
>

Vanessa,

1st - congrats!

2nd - I think those parts have gone obsolete at lattice semi :(  But, it 
looks like atmel has them and also TI (quick check on digikey).

Yes, the great thing about HDL is the tools are probably going to be 
much better at deMorgan than most people.  They *usually* generate 
pretty efficient stuff - not always though.  But the beauty is you write 
the code as it makes the most sense to you.  The synthesis tools do all 
the heavy work.  If you find it doesn't fit, you can play games to optimize.

A couple of code suggestions:

You wrote:

always @(posedge Phi2_Inv_In) begin
   if (A1 & A2 & ~A0 & ~RW & ~IO2) CASBankSel <= D3;
   Q <= ~RAS0In & CAS0In;
end

But do not explicitly say what to do for the else portion. For example:

always @(posedge Phi2_Inv_In) begin
   if (A1 & A2 & ~A0 & ~RW & ~IO2)
	CASBankSel <= D3;
   else
	CASBankSel <= CASBankSel;

   Q <= ~RAS0In & CAS0In;
end


Oh, and you have no reset state.  Maybe a problem, maybe not - depends 
on the design.  As far as I can see, your 2 flip-flops will power up as 
the chip likes.  Some FPGA's have built-in default power up state but 
it's bad practice to rely on it.  Just a suggestion.

Anyway - have fun with it.

gene