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Date: Fri, 29 Jan 2016 04:31:21 +0100 (CET)
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Subject: Re: [geda-user] The nature of gEDA layers
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On Thu, 28 Jan 2016, Britton Kerin (britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com] wrote:

> It's highly unlikely it'll be easier for just BBVias.  I believe
> there's already an experimental branch that implements them.  Igor is
> likely to decide to implement them again while we all talk about it.

pcb-rnd:

Not unless at least 4 active users sign up for testing it in pcb-rnd. And 
this is very unlikely to happen.

mainline pcb:

As of now I think the smoke around BBVias is much bigger than the flame. I 
mean there are a lot of people investing hours a day mailing about it but 
I don't see too many of them would sit down to code or seriously test 
code.

And testing this one is no joy: a lot of ugly corner cases, have to 
figure how to export BB, have to actually send exports to fab houses to 
find out whether the export really works, risking getting back some broken 
boards along the road in the early phase, etc. To me this doesn't seem 
like a one-man show.

If I was a PCB developer or PCB power user, I'd do a poll for pcb similar 
to the one I did for pcb-rnd and I would try to gather actual 
contributors. Depending on the scale of the refactoring you go for:

- 1..5 programmers. I really believe the feature can be adde without any 
serious change of the current infra, and that'd be the 1 programmer setup 
I planned for pcb-rnd. The other extreme is a full redesign of all 
internals which I can't believe could be finished within reasonable time 
frame with less than 5 programmers as we are not talking about full time 
programmers here. Such a project would touch every other line of the code 
so it's not like a git branch evolving for some months or years then 
merged^1 back to master - rather like a brand new mainline and then a lot 
of hassle to merge^1 all the other branches into it.

- a handful of testers, to make sure all possible combination of gui 
features, printing, autorouting, rats/find.c connection testing, exotic 
netlist change imports, layer^2 stackup changes, save/load corners, etc 
work properly - so that at least the pure software side didn't break

- at least 2..3 users who are willing to experiment with sending 
their next board to their favorite fab house with a small BB pattern 
sitting in a corner to see if it really worked. I guess they'd also have 
to invest some money: the price gap between normal board and the BB thing 
for that batch.

Honestly, in case of geda-user, I am highly skeptic about converting hours 
spent on mailing into hours spent on any of the above three. My current 
bet is on a few new pcb branches/forks aiming for some large scale rewrite 
then given up after some weeks or months, leaving mainline pcb without 
BBvias. No offense meant; and of course I may be just too grumpy here.

Regards,

Igor2


NO-FLAME DISCLAIMER:

^1: I used word "merge" as in getting the two diverging code together. I 
don't care how it's technically done and what name your favorite VCS has 
for the actual process.

^2: Layer as pcb defines it today. If you like renaming things, just use 
sed to replace the word layer to whatever else you prefer before reading 
my mail, but please don't reply just to add some noise about the word 
"layer".