X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Date: Fri, 22 Jan 2016 20:20:08 +0100 (CET) From: Roland Lutz To: "Bert Timmerman (bert DOT timmerman AT xs4all DOT nl) [via geda-user AT delorie DOT com]" Subject: Re: [geda-user] PCB data structures In-Reply-To: <56A1C4AE.9010703@xs4all.nl> Message-ID: References: <1512221837 DOT AA25291 AT ivan DOT Harhan DOT ORG> <20160106143629 DOT 4D39D809D79B AT turkos DOT aspodata DOT se> <20160106164022 DOT D0D4E809D79B AT turkos DOT aspodata DOT se> <20160106180912 DOT 42ddf4079d91384f206b7c35 AT gmail DOT com> <20160106191433 DOT 5dc5cb59 AT jive DOT levalinux DOT org> <20160106202817 DOT 56197b2c539d426a1b724c9e AT gmail DOT com> <568E09ED DOT 1080508 AT m0n5t3r DOT info> <568E6354 DOT 80302 AT m0n5t3r DOT info> <20160108002640 DOT 03233b24 AT jive DOT levalinux DOT org> <20160108175259 DOT 127a3f073616758434f7edff AT gmail DOT com> <20160109020345 DOT 1e07cb84 AT jive> <20160109112851 DOT 1129dc38 AT wind DOT levalinux DOT org> <56A1C4AE DOT 9010703 AT xs4all DOT nl> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; format=flowed; charset=US-ASCII Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Fri, 22 Jan 2016, Bert Timmerman (bert DOT timmerman AT xs4all DOT nl) [via geda-user AT delorie DOT com] wrote: > AFAICT a via lives on board level. I checked, you're right. Thanks for the correction. :) I noticed that this applies to rats, too. While thinking about it, I'm not sure if a layout layer can contain pad and pin objects. The documentation says that "footprints are created graphically by placing pads and then converting a group of pads to a component", but it also says "for surface mount pads, draw line segments". > All the via_pads beloging to a via have all the same > location/dimensions/connectivity and are switched on/off per layer level > inside the via definition. Are you referring to PCB data structures or the file format?