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Subject: Re: [geda-user] Project leadership (generic, buses)
From: "Svenn Are Bjerkem (svenn DOT bjerkem AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On 29 December 2015 at 09:25, Nicklas Karlsson
(nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]
<geda-user AT delorie DOT com> wrote:
> Then it is certainly very generic: ASIC, Circuit boards, cables connecting circuit boards, Verilog, VHDL?

I have been following gschem since late 90's and didn't know about
Paul Tan's efforts until John made me aware. I am now looking into
Paul's work to understand how he implements bus pins and unnamed bus
connections in gschem. I have so far found that Paul has created a
bash script in contrib/scripts which is so well documented that I
graps what the script is doing. That is seldom the case of a bash
script.
Paul is relying on a lot of low level work on the files and the stock
verilog backend in gnetlist. That backend seems to understand verilog
bus notation in netnames by regexp. Paul's workflow set some hard
requirements on required attributes to make the flow work. From what I
see, Paul has not done any work on gschem code to make said bus
functionality work, but I may have missed something.

To make the same functionality for VHDL, the gnetlist vhdl backend
functionality must track the verilog backend if a designer would like
to switch from verilog netlist to vhdl netlist just by switching the
gnetlist backend.
My use of gschem is not at gate level, it is at block level, and here
the need for quick and reliable connection of wide buses is key for
efficient use.

In my view it is only generic if all backends do exactly the same text
processing and use exactly the same attribute names. I don't think
that is generic enough. But I may be wrong.

-- 
Svenn