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From: geda AT psjt DOT org (Stephan =?utf-8?Q?B=C3=B6ttcher?=)
To: <geda-user AT delorie DOT com>
Subject: Re: [geda-user] Project leadership
References: <1512221837 DOT AA25291 AT ivan DOT Harhan DOT ORG>
	<CAJXU7q_mXmipJ1fLvLpuLvnYjktV2SHoA+bG=L5+E-EfdygeOA AT mail DOT gmail DOT com>
Date: Tue, 22 Dec 2015 22:33:01 +0100
In-Reply-To: <CAJXU7q_mXmipJ1fLvLpuLvnYjktV2SHoA+bG=L5+E-EfdygeOA@mail.gmail.com>
	(Peter Clifton's message of "Tue, 22 Dec 2015 20:09:03 +0000")
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"Peter Clifton (petercjclifton AT googlemail DOT com) [via
geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> writes:

> I really believe you are on to a very strong concept here...
> schematics have their place IMO, but look at many modern designs
> (laptop etc., say?) and see how that graphical the format of
> schematics is really being pushed beyond its most effective.

People tell me that a schematic drawing should illustrate the function
of a circuit.  But most of that function is hidden inside the µC and
FPGA.  So, my symbols and schematics are more a preview of the layout,
to get a good first shot at (functionally arbitrary) pin assignements.

Like this one:  http://www.ieap.uni-kiel.de/et/people/stephan/rpirena/

I thought about using Verilog as netlist format for PCBs.  How would I
convert those to pcb netlists, with some graphical drawings added in the
mix?

 gschem, gnetlist --> Verilog
 Verilog --> ueda --> PCB netlist

?

-- 
Stephan