X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Envelope-From: paubert AT iram DOT es Date: Mon, 13 Jul 2015 20:00:00 +0200 From: "Gabriel Paubert (paubert AT iram DOT es) [via geda-user AT delorie DOT com]" To: geda-user AT delorie DOT com Subject: Re: [geda-user] gEDA/gschem still alive? Message-ID: <20150713180000.GB28925@visitor2.iram.es> References: <1436287952 DOT 678 DOT 26 DOT camel AT ssalewski DOT de> <559C0F7E DOT 7010009 AT neurotica DOT com> <1436295556 DOT 678 DOT 91 DOT camel AT ssalewski DOT de> <559C3778 DOT 4000105 AT neurotica DOT com> <20150708072021 DOT GB13243 AT visitor2 DOT iram DOT es> <20150713082342 DOT GB26809 AT visitor2 DOT iram DOT es> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Spamina-Bogosity: Unsure X-Spamina-Spam-Score: -1.0 (-) X-Spamina-Spam-Report: Content analysis details: (-1.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 URIBL_BLOCKED ADMINISTRATOR NOTICE: The query to URIBL was blocked. See http://wiki.apache.org/spamassassin/DnsBlocklists#dnsbl-block for more information. [URIs: iram.es] -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP -0.0 BAYES_20 BODY: Bayes spam probability is 5 to 20% [score: 0.1747] Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Mon, Jul 13, 2015 at 08:50:10AM -0600, John Doty wrote: > > On Jul 13, 2015, at 2:23 AM, Gabriel Paubert (paubert AT iram DOT es) [via geda-user AT delorie DOT com] wrote: > > > The common point I see right now between these schematics is that > > they have symbols with lots of pins. For components with a large number > > of pins, I always split the part in several, easier to manage symbols, > > except for the power supply part. > > For things with a lot of pins, I usually just draw a box without pins, run a bus to it, and make the pin connections from a table with pins2gsch.awk. I get that into the documentation with pins2tex.awk. Diagrams are great for amplifiers and filters, but not very illuminating for complicated digital stuff. For me, a nicely-formatted table is a lot easier to read than a big mess of lines converging on a box. > That's not very useful for what I do, I'm using a chip where the recommended decoupling is 3 capacitors for every pair of power pins (ground goes mostly through the central paddle). The capacitors take well more space on the schematics than the rectangle for the symbol that that describes that part of the component. Note that the rest of the component is split into manageable symbols (most are below 10 pins, although I only really start to worry above 16, although some go higher). Most of the symbols I create are unique to each project (always for FPGA), and the pins are ordered to minimize (actually almost eliminate) crossings on the schematics. Gabriel