X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:content-type; bh=IQ/9vlJwE+P8VToY9gXfdNUa0pkHYiBfPTR8lg8VgzM=; b=IpmXNLOcLQy+Oqtm3nHqnr4/wDhWayGck8G/U1rkWTaO+3nag/TQ18RmcqRj0rgq0S xnN9eWB1uLqdn95hGhEuTeZiBU2Ew59QaneOoyLawdvrm/H60qNWPNeXXp8OES3P/Ro6 iHIaJ212XniUDsF83OtwfD2GnWSMVFjG1UUrYOH/I72n94gu+kZnoSA8W5XbK+6EkjD2 pThvBhAplLvoSuuKCJErx9H0OByqwSE4M8PO4/ej+GF9KPVeZgf1396IzHIZVOaMq4ba GJHJnMiIanUm9meXCy5FiAgpLor9s4OwTB0RVWb9nvM5LqSXlCWwEBmx0y11Y9i+l7HV AjLA== X-Gm-Message-State: ALoCoQlMowz7lfzb8JPGoM4RQxQ+LvEvCjui0IBia2wSe45oURo4ltIm2+364dFdO3Q2kztCCBHE X-Received: by 10.180.20.33 with SMTP id k1mr10362215wie.21.1378056568819; Sun, 01 Sep 2013 10:29:28 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20130901043811.GA18909@recycle.lbl.gov> References: <20130901043811 DOT GA18909 AT recycle DOT lbl DOT gov> From: Joshua Lansford Date: Sun, 1 Sep 2013 13:29:08 -0400 Message-ID: Subject: Re: [geda-user] VE To: geda-user AT delorie DOT com Content-Type: multipart/alternative; boundary=bcaec53d5ee143e20404e555cce1 Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk --bcaec53d5ee143e20404e555cce1 Content-Type: text/plain; charset=ISO-8859-1 > > > I don't see any Makefile or README files > I will try to quickly create a README with instructions on how to compile and run. > > > Currently all the vars are stuck at 32 bits, but Verilog > > synthesizers generally get rid of unused bits anyway. > > I don't understand that statement. I'm very interested in being > able to write generic numeric code, have it simulate (at first) > at "infinite" precision, then establish real-life bounds and precision > needs based on SNR goals, resulting in concrete scaled-fixed-point > variables. That is well beyond existing language capabilities. > I see. Each var should be able to be declared with a specified number of bits, hopefully including floating point. Currently it is hardwired to 32. Infinite precision perhaps would be best simulated before Verilog compilation but this does not exist yet. > > I am not aware of any other > > open source project working in this direction. > > Another possibly related project is migen > https://github.com/milkymist/migen > > Ok, Thanks. --bcaec53d5ee143e20404e555cce1 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable

I don't see any Makefile or README files=A0

I will try to quickly create a=A0README=A0with instructions = on how to compile and run.

> Currently all the vars are stuck at 32 bits, but Verilog
> synthesizers generally get rid of unused bits anyway.

I don't understand that statement. =A0I'm very interested in = being
able to write generic numeric code, have it simulate (at first)
at "infinite" precision, then establish real-life bounds and prec= ision
needs based on SNR goals, resulting in concrete scaled-fixed-point
variables. =A0That is well beyond existing language capabilities.

I see. =A0Each var should be able to= be declared with a specified number of bits,=A0hopefully=A0including float= ing point. =A0Currently it is hardwired to 32. =A0Infinite=A0precision=A0pe= rhaps would be best simulated before=A0Verilog=A0compilation but this does = not exist=A0yet.

=A0I am not aware of any other
> open source project working in this direction.

Another possibly related project is migen
https://gi= thub.com/milkymist/migen

Ok, Thanks.

--bcaec53d5ee143e20404e555cce1--